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2020 – today
- 2023
[j26]Eesa Nikahd
, Morteza Saheb Zamani, Mehdi Sedighi:
Low-overhead code concatenation approaches for universal quantum computation. Quantum Inf. Process. 22(1): 73 (2023)- 2022
- [j25]Mohammad Hadi Mottaghi, Mehdi Sedighi, Morteza Saheb Zamani:
FIFA: A Fully Invertible FPGA Architecture to Reduce BTI-Induced Aging Effects. IEEE Trans. Computers 71(9): 2277-2286 (2022) - 2021
- [j24]Amir Bavafa Toosi, Mehdi Sedighi:
FERMAT: FPGA energy reduction method by approximation theory. J. Supercomput. 77(9): 9721-9745 (2021) - 2020
- [j23]Mona Arabzadeh, Mehdi Sedighi, Morteza Saheb Zamani, Sayed-Amir Marashi:
A system architecture for parallel analysis of flux-balanced metabolic pathways. Comput. Biol. Chem. 88: 107309 (2020) - [j22]Mohammad Hadi Mottaghi, Mehdi Sedighi, Morteza Saheb Zamani:
Aging Mitigation in FPGAs Considering Delay, Power, and Temperature. IEEE Trans. Reliab. 69(2): 833-844 (2020)
2010 – 2019
- 2018
- [j21]Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi, Sayed-Amir Marashi:
A graph-based approach to analyze flux-balanced pathways in metabolic networks. Biosyst. 165: 40-51 (2018) - 2017
- [j20]Samaneh Emami, Mehdi Sedighi:
An optimized reconfigurable architecture for hardware implementation of decimal arithmetic. Comput. Electr. Eng. 63: 18-29 (2017) - [j19]Behrouz Zolfaghari, Mehran S. Fallah, Mehdi Sedighi:
S-Restricted Compositions Revisited. Discret. Math. Theor. Comput. Sci. 19(1) (2017) - [j18]Mahboobeh Houshmand, Mehdi Sedighi, Morteza Saheb Zamani, Kourosh Marjoei:
Quantum Circuit Synthesis Targeting to Improve One-Way Quantum Computation Pattern Cost Metrics. ACM J. Emerg. Technol. Comput. Syst. 13(4): 55:1-55:27 (2017) - [i8]Maryam Eslamy, Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi:
Geometry-Based Optimization of One-Way Quantum Computation Measurement Patterns. CoRR abs/1704.07378 (2017) - 2016
- [j17]Mona Arabzadeh, Mahboobeh Houshmand, Mehdi Sedighi, Morteza Saheb Zamani:
Quantum-Logic Synthesis of Hermitian Gates. ACM J. Emerg. Technol. Comput. Syst. 12(4): 40:1-40:15 (2016) - [c23]Mohammad Reza Bagheri, Reza Gholami, Sohrab Mortazavi Ghalati, Mehdi Sedighi:
Location-based scheduling: An approach to address challenges of Big Data and Mobile Cloud Computing. IST 2016: 700-706 - [i7]Eesa Nikahd, Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi:
One-Way Quantum Computer Simulation. CoRR abs/1604.05659 (2016) - 2015
- [j16]Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi, Monireh Houshmand:
GA-based approach to find the stabilizers of a given sub-space. Genet. Program. Evolvable Mach. 16(1): 57-71 (2015) - [j15]Eesa Nikahd, Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi:
One-way quantum computer simulation. Microprocess. Microsystems 39(3): 210-222 (2015) - [c22]Mehdi Sedighi, Foroogh Haddadi, Samaneh Emami, Mahya Saffarpour:
A heuristic algorithm for high level synthesis of decimal arithmetic circuits using SystemC. DTIS 2015: 1-6 - 2014
- [j14]Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi, Mona Arabzadeh:
Decomposition of Diagonal Hermitian Quantum Gates Using Multiple-Controlled Pauli Z Gates. ACM J. Emerg. Technol. Comput. Syst. 11(3): 28:1-28:10 (2014) - [j13]Naser MohammadZadeh, Morteza Saheb Zamani, Mehdi Sedighi:
Quantum circuit physical design methodology with emphasis on physical synthesis. Quantum Inf. Process. 13(2): 445-465 (2014) - [j12]Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi, Mohammad Hossein Samavatian:
Automatic translation of quantum circuits to optimized one-way quantum computation patterns. Quantum Inf. Process. 13(11): 2463-2482 (2014) - [i6]Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi, Mona Arabzadeh:
Decomposition of Diagonal Hermitian Quantum Gates Using Multiple-Controlled Pauli Z Gates. CoRR abs/1405.6741 (2014) - 2013
- [j11]Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi, Mehdi Saeedi:
Depth-optimized reversible circuit synthesis. Quantum Inf. Process. 12(4): 1677-1699 (2013) - [j10]Maryam Yazdani, Morteza Saheb Zamani, Mehdi Sedighi:
A quantum physical design flow using ILP and graph drawing. Quantum Inf. Process. 12(10): 3239-3264 (2013) - [i5]Maryam Yazdani, Morteza Saheb Zamani, Mehdi Sedighi:
A Quantum Physical Design Flow Using ILP and Graph Drawing. CoRR abs/1306.2037 (2013) - 2012
- [c21]Eesa Nikahd, Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi:
OWQS: One-Way Quantum Computation Simulator. DSD 2012: 98-104 - [c20]Mehdi Harounabadi, Mehdi Sedighi:
A fast response dynamic bandwidth allocation algorithm for a converged EPON and WiMAX network. IST 2012: 470-476 - [i4]Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi, Mehdi Saeedi:
Depth-Optimized Reversible Circuit Synthesis. CoRR abs/1208.5425 (2012) - 2011
- [j9]Hamid Hassanpour, Mehdi Sedighi, Ali Reza Manashty:
Video Frame's Background Modeling: Reviewing the Techniques. J. Signal Inf. Process. 2(2): 72-78 (2011) - [j8]Mehdi Saeedi, Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi:
Block-based quantum-logic synthesis. Quantum Inf. Comput. 11(3&4): 262-277 (2011) - [j7]Naser MohammadZadeh, Morteza Saheb Zamani, Mehdi Sedighi:
Auxiliary qubit selection: a physical synthesis technique for quantum circuits. Quantum Inf. Process. 10(2): 139-154 (2011) - 2010
- [j6]Mehdi Sedighi, Sam Farrokhi:
GALS system optimization using retiming concept. IEICE Electron. Express 7(3): 209-215 (2010) - [j5]Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi, Zahra Sasanian:
Reversible circuit synthesis using a cycle-based approach. ACM J. Emerg. Technol. Comput. Syst. 6(4): 13:1-13:26 (2010) - [j4]Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani:
A library-based synthesis methodology for reversible logic. Microelectron. J. 41(4): 185-194 (2010) - [j3]Naser MohammadZadeh, Mehdi Sedighi, Morteza Saheb Zamani:
Quantum physical synthesis: Improving physical design by netlist modifications. Microelectron. J. 41(4): 219-230 (2010) - [i3]Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani:
A Library-Based Synthesis Methodology for Reversible Logic. CoRR abs/1004.1697 (2010) - [i2]Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi, Zahra Sasanian:
Reversible Circuit Synthesis Using a Cycle-Based Approach. CoRR abs/1004.4320 (2010) - [i1]Mehdi Saeedi, Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi:
Block-based quantum-logic synthesis. CoRR abs/1011.2159 (2010)
2000 – 2009
- 2009
- [c19]Zahra Sasanian, Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani:
A cycle-based synthesis algorithm for reversible logic. ASP-DAC 2009: 745-750 - [c18]Naser MohammadZadeh, Morteza Saheb Zamani, Mehdi Sedighi:
Improving Latency of Quantum Circuits by Gate Exchanging. DSD 2009: 67-73 - 2008
- [j2]Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani:
Synthesis of reversible circuits using a moving forward strategy. IEICE Electron. Express 5(17): 638-643 (2008) - [c17]Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi:
Moving forward: A non-search based synthesis method toward efficient CNOT-based quantum circuit synthesis algorithms. ASP-DAC 2008: 83-88 - [c16]Mehdi Saeedi, Naser MohammadZadeh, Mehdi Sedighi, Morteza Saheb Zamani:
Evaluation and Improvement of Quantum Synthesis Algorithms based on a Thorough Set of Metrics. DSD 2008: 490-493 - [c15]Ehsan K. Ardestani, Morteza Saheb Zamani, Mehdi Sedighi:
A Fast Transformation-Based Synthesis Algorithm for Reversible Circuits. DSD 2008: 803-806 - [c14]Mahdi Aminian, Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi:
FPGA-Based Circuit Model Emulation of Quantum Algorithms. ISVLSI 2008: 399-404 - 2007
- [c13]Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi:
Algebraic Characterization of CNOT-Based Quantum Circuits with its Applications on Logic Synthesis. DSD 2007: 339-346 - [c12]Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani:
A novel synthesis algorithm for reversible circuits. ICCAD 2007: 65-68 - [c11]Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi:
On the Behavior of Substitution-based Reversible Circuit Synthesis Algorithms: Investigation and Improvement. ISVLSI 2007: 428-436 - 2006
- [j1]Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi:
An integrated temporal partitioning and physical design framework for static compilation of reconfigurable computing systems. Microprocess. Microsystems 30(1): 52-62 (2006) - [c10]Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki J. Murakami, Mehdi Sedighi, Koji Inoue:
An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit. Asia-Pacific Computer Systems Architecture Conference 2006: 219-230 - [c9]Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi, Kazuaki J. Murakami, Hamid Noori:
GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs. ERSA 2006: 227-230 - [c8]Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki J. Murakami, Koji Inoue, Mehdi Sedighi:
Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit. EUC 2006: 722-731 - [c7]M. Rahmaniheris, Mehdi Sedighi:
A New Algorithm for Resource Manager to Enhance the Quality of Service in VoIP Systems. ICN/ICONS/MCL 2006: 2 - [c6]Farhad Mehdipour, Morteza Saheb Zamani, Hamid Reza Ahmadifar, Mehdi Sedighi, Kazuaki J. Murakami:
Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework. IPDPS 2006 - 2005
- [c5]Hamid Safizadeh, Hamid Noori, Mehdi Sedighi, Ali Jahanian, Neda Zolfaghari:
Efficient Host-Independent Coprocessor Architecture for Speech Coding Algorithms. DSD 2005: 227-230 - [c4]Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi:
Reducing Inter-Configuration Memory Usage and Performance Improvement in Reconfigurable Computing Systems. DSD 2005: 372-378 - [c3]Mehrdad Najibi, Kamran Saleh, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi:
Prototyping globally asynchronous locally synchronous circuits on commercial synchronous FPGAs (abstract only). FPGA 2005: 269 - [c2]Kamran Saleh, Mehrdad Najibi, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi:
A novel clock generation scheme for globally asynchronous locally synchronous systems: an FPGA-validated approach. ACM Great Lakes Symposium on VLSI 2005: 296-301 - [c1]Mehrdad Najibi, Kamran Saleh, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi:
Prototyping Globally Asynchronous Locally Synchronous Circuits on Commercial Synchronous FPGAs. IEEE International Workshop on Rapid System Prototyping 2005: 63-69
Coauthor Index
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