iBet uBet web content aggregator. Adding the entire web to your favor.
iBet uBet web content aggregator. Adding the entire web to your favor.



Link to original content: https://dblp.org/pid/06/0.rss
dblp: Ahmed Rezine https://dblp.org/pid/06/0.html dblp person page RSS feed Wed, 23 Oct 2024 20:33:26 +0200 en-US daily 1 released under the CC0 1.0 license dblp@dagstuhl.de (dblp team) dblp@dagstuhl.de (dblp team) Computers/Computer_Science/Publications/Bibliographies http://www.rssboard.org/rss-specification https://dblp.org/img/logo.144x51.pngdblp: Ahmed Rezinehttps://dblp.org/pid/06/0.html14451 On Modeling and Detecting Trojans in Instruction Sets.https://doi.org/10.1109/TCAD.2024.3389558, , , , , , , , :
On Modeling and Detecting Trojans in Instruction Sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(10): 3226-3239 ()]]>https://dblp.org/rec/journals/tcad/ZhangHLRPLYJL24Tue, 01 Oct 2024 01:00:00 +0200 VNN: Verification-Friendly Neural Networks with Hard Robustness Guarantees.https://openreview.net/forum?id=gUFufRkzjV, , :
VNN: Verification-Friendly Neural Networks with Hard Robustness Guarantees. ICML ]]>https://dblp.org/rec/conf/icml/BaninajjarRA24Mon, 01 Jan 2024 00:00:00 +0100 Verified Relative Safety Margins for Neural Network Twins.https://doi.org/10.48550/arXiv.2409.16726, , , :
Verified Relative Safety Margins for Neural Network Twins. CoRR abs/2409.16726 ()]]>https://dblp.org/rec/journals/corr/abs-2409-16726Mon, 01 Jan 2024 00:00:00 +0100 SafeDeep: A Scalable Robustness Verification Framework for Deep Neural Networks.https://doi.org/10.1109/ICASSP49357.2023.10097028, , , :
SafeDeep: A Scalable Robustness Verification Framework for Deep Neural Networks. ICASSP : 1-5]]>https://dblp.org/rec/conf/icassp/BaninajjarHRA23Sun, 01 Jan 2023 00:00:00 +0100 Verification-Friendly Deep Neural Networks.https://doi.org/10.48550/arXiv.2312.09748, , :
Verification-Friendly Deep Neural Networks. CoRR abs/2312.09748 ()]]>https://dblp.org/rec/journals/corr/abs-2312-09748Sun, 01 Jan 2023 00:00:00 +0100 Symbolic identification of shared memory based bank conflicts for GPUs.https://doi.org/10.1016/j.sysarc.2022.102518, , , , :
Symbolic identification of shared memory based bank conflicts for GPUs. J. Syst. Archit. 127: 102518 ()]]>https://dblp.org/rec/journals/jsa/HorgaRCEP22Sat, 01 Jan 2022 00:00:00 +0100 Breaking Silos to Guarantee Control Stability with Communication over Ethernet TSN.https://doi.org/10.1109/MDAT.2020.2968281, , , , , :
Breaking Silos to Guarantee Control Stability with Communication over Ethernet TSN. IEEE Des. Test 38(5): 48-56 ()]]>https://dblp.org/rec/journals/dt/MahfouziASREP21Fri, 01 Jan 2021 00:00:00 +0100 Correction to: An integrated specification and verification technique for highly concurrent data structures.https://doi.org/10.1007/s10009-021-00629-9, , , , :
Correction to: An integrated specification and verification technique for highly concurrent data structures. Int. J. Softw. Tools Technol. Transf. 23(5): 825 ()]]>https://dblp.org/rec/journals/sttt/AbdullaHHJR21Fri, 01 Jan 2021 00:00:00 +0100 Software-Based Self-Testing Using Bounded Model Checking for Out-of-Order Superscalar Processors.https://doi.org/10.1109/TCAD.2018.2890695, , , , , , :
Software-Based Self-Testing Using Bounded Model Checking for Out-of-Order Superscalar Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(3): 714-727 ()]]>https://dblp.org/rec/journals/tcad/ZhangCPRLEJ20Wed, 01 Jan 2020 00:00:00 +0100 Verifying Safety of Parameterized Heard-Of Algorithms.https://doi.org/10.1007/978-3-030-67087-0_14, , , :
Verifying Safety of Parameterized Heard-Of Algorithms. NETYS : 209-226]]>https://dblp.org/rec/conf/netys/GanjeiREP20Wed, 01 Jan 2020 00:00:00 +0100 Quantifying the Information Leakage in Cache Attacks via Symbolic Execution.https://doi.org/10.1145/3288758, , , :
Quantifying the Information Leakage in Cache Attacks via Symbolic Execution. ACM Trans. Embed. Comput. Syst. 18(1): 7:1-7:27 ()]]>https://dblp.org/rec/journals/tecs/ChattopadhyayBR19Tue, 01 Jan 2019 00:00:00 +0100 On Reachability in Parameterized Phaser Programs.https://doi.org/10.1007/978-3-030-17462-0_17, , , , :
On Reachability in Parameterized Phaser Programs. TACAS (1) : 299-315]]>https://dblp.org/rec/conf/tacas/GanjeiRHEP19Tue, 01 Jan 2019 00:00:00 +0100 Stability-aware integrated routing and scheduling for control applications in Ethernet networks.https://doi.org/10.23919/DATE.2018.8342096, , , , , :
Stability-aware integrated routing and scheduling for control applications in Ethernet networks. DATE : 682-687]]>https://dblp.org/rec/conf/date/MahfouziASREP18Mon, 01 Jan 2018 00:00:00 +0100 Trau: SMT solver for string constraints.https://doi.org/10.23919/FMCAD.2018.8602997, , , , , , :
Trau: SMT solver for string constraints. FMCAD : 1-5]]>https://dblp.org/rec/conf/fmcad/AbdullaACDHRR18Mon, 01 Jan 2018 00:00:00 +0100 On Reachability in Parameterized Phaser Programs.http://arxiv.org/abs/1811.07142, , , , :
On Reachability in Parameterized Phaser Programs. CoRR abs/1811.07142 ()]]>https://dblp.org/rec/journals/corr/abs-1811-07142Mon, 01 Jan 2018 00:00:00 +0100 An integrated specification and verification technique for highly concurrent data structures.https://doi.org/10.1007/s10009-016-0415-4, , , , :
An integrated specification and verification technique for highly concurrent data structures. Int. J. Softw. Tools Technol. Transf. 19(5): 549-563 ()]]>https://dblp.org/rec/journals/sttt/AbdullaHHJR17Sun, 01 Jan 2017 00:00:00 +0100 Safety verification of phaser programs.https://doi.org/10.23919/FMCAD.2017.8102243, , , :
Safety verification of phaser programs. FMCAD : 68-75]]>https://dblp.org/rec/conf/fmcad/GanjeiREP17Sun, 01 Jan 2017 00:00:00 +0100 Quantifying the information leak in cache attacks via symbolic execution.https://doi.org/10.1145/3127041.3127044, , , :
Quantifying the information leak in cache attacks via symbolic execution. MEMOCODE : 25-35]]>https://dblp.org/rec/conf/memocode/ChattopadhyayBR17Sun, 01 Jan 2017 00:00:00 +0100 Flatten and conquer: a framework for efficient analysis of string constraints.https://doi.org/10.1145/3062341.3062384, , , , , , :
Flatten and conquer: a framework for efficient analysis of string constraints. PLDI : 602-617]]>https://dblp.org/rec/conf/pldi/AbdullaACDHRR17Sun, 01 Jan 2017 00:00:00 +0100 Safety Verification of Phaser Programs.http://arxiv.org/abs/1708.02801, , , :
Safety Verification of Phaser Programs. CoRR abs/1708.02801 ()]]>https://dblp.org/rec/journals/corr/abs-1708-02801Sun, 01 Jan 2017 00:00:00 +0100 Counting dynamically synchronizing processes.https://doi.org/10.1007/s10009-015-0411-0, , , :
Counting dynamically synchronizing processes. Int. J. Softw. Tools Technol. Transf. 18(5): 517-534 ()]]>https://dblp.org/rec/journals/sttt/GanjeiREP16Fri, 01 Jan 2016 00:00:00 +0100 Lazy Constrained Monotonic Abstraction.https://doi.org/10.1007/978-3-662-49122-5_7, , , :
Lazy Constrained Monotonic Abstraction. VMCAI : 147-165]]>https://dblp.org/rec/conf/vmcai/GanjeiREP16Fri, 01 Jan 2016 00:00:00 +0100 Quantifying the Information Leak in Cache Attacks through Symbolic Execution.http://arxiv.org/abs/1611.04426, , , :
Quantifying the Information Leak in Cache Attacks through Symbolic Execution. CoRR abs/1611.04426 ()]]>https://dblp.org/rec/journals/corr/ChattopadhyayBR16Fri, 01 Jan 2016 00:00:00 +0100 Norn: An SMT Solver for String Constraints.https://doi.org/10.1007/978-3-319-21690-4_29, , , , , , :
Norn: An SMT Solver for String Constraints. CAV (1) : 462-469]]>https://dblp.org/rec/conf/cav/AbdullaACHRRS15Thu, 01 Jan 2015 00:00:00 +0100 Verification of Cache Coherence Protocols wrt. Trace Filters.https://doi.org/10.1109/FMCAD.2015.7542247, , , , :
Verification of Cache Coherence Protocols wrt. Trace Filters. FMCAD : 9-16]]>https://dblp.org/rec/conf/fmcad/AbdullaAGRZ15Thu, 01 Jan 2015 00:00:00 +0100 Abstracting and Counting Synchronizing Processes.https://doi.org/10.1007/978-3-662-46081-8_13, , , :
Abstracting and Counting Synchronizing Processes. VMCAI : 227-244]]>https://dblp.org/rec/conf/vmcai/GanjeiREP15Thu, 01 Jan 2015 00:00:00 +0100 String Constraints for Verification.https://doi.org/10.1007/978-3-319-08867-9_10, , , , , , :
String Constraints for Verification. CAV : 150-166]]>https://dblp.org/rec/conf/cav/AbdullaACHRRS14Wed, 01 Jan 2014 00:00:00 +0100 Ordered Counter-Abstraction - Refinable Subword Relations for Parameterized Verification.https://doi.org/10.1007/978-3-319-04921-2_32, :
Ordered Counter-Abstraction - Refinable Subword Relations for Parameterized Verification. LATA : 396-408]]>https://dblp.org/rec/conf/lata/GantyR14Wed, 01 Jan 2014 00:00:00 +0100 Verifying safety and liveness for the FlexTM hybrid transactional memory.https://doi.org/10.7873/DATE.2013.167, , , , :
Verifying safety and liveness for the FlexTM hybrid transactional memory. DATE : 785-790]]>https://dblp.org/rec/conf/date/AbdullaDRSZ13Tue, 01 Jan 2013 00:00:00 +0100 An Integrated Specification and Verification Technique for Highly Concurrent Data Structures.https://doi.org/10.1007/978-3-642-36742-7_23, , , , :
An Integrated Specification and Verification Technique for Highly Concurrent Data Structures. TACAS : 324-338]]>https://dblp.org/rec/conf/tacas/AbdullaHHJR13Tue, 01 Jan 2013 00:00:00 +0100 Memorax, a Precise and Sound Tool for Automatic Fence Insertion under TSO.https://doi.org/10.1007/978-3-642-36742-7_37, , , , :
Memorax, a Precise and Sound Tool for Automatic Fence Insertion under TSO. TACAS : 530-536]]>https://dblp.org/rec/conf/tacas/AbdullaACLR13Tue, 01 Jan 2013 00:00:00 +0100 A lightweight regular model checking approach for parameterized systems.https://doi.org/10.1007/s10009-011-0213-y, :
A lightweight regular model checking approach for parameterized systems. Int. J. Softw. Tools Technol. Transf. 14(2): 207-222 ()]]>https://dblp.org/rec/journals/sttt/DelzannoR12Sun, 01 Jan 2012 00:00:00 +0100 Automatic Test Program Generation for Out-of-Order Superscalar Processors.https://doi.org/10.1109/ATS.2012.43, , , :
Automatic Test Program Generation for Out-of-Order Superscalar Processors. Asian Test Symposium : 338-343]]>https://dblp.org/rec/conf/ats/ZhangREP12Sun, 01 Jan 2012 00:00:00 +0100 Detecting Key Players in Terrorist Networks.https://doi.org/10.1109/EISIC.2012.13, , :
Detecting Key Players in Terrorist Networks. EISIC : 297-302]]>https://dblp.org/rec/conf/eisic/BerzinjiKR12Sun, 01 Jan 2012 00:00:00 +0100 Automatic Fence Insertion in Integer Programs via Predicate Abstraction.https://doi.org/10.1007/978-3-642-33125-1_13, , , , :
Automatic Fence Insertion in Integer Programs via Predicate Abstraction. SAS : 164-180]]>https://dblp.org/rec/conf/sas/AbdullaACLR12Sun, 01 Jan 2012 00:00:00 +0100 Counter-Example Guided Fence Insertion under TSO.https://doi.org/10.1007/978-3-642-28756-5_15, , , , :
Counter-Example Guided Fence Insertion under TSO. TACAS : 204-219]]>https://dblp.org/rec/conf/tacas/AbdullaACLR12Sun, 01 Jan 2012 00:00:00 +0100 Proceedings 14th International Workshop on Verification of Infinite-State Systems, Infinity 2012, Paris, France, 27th August 2012.https://doi.org/10.4204/EPTCS.107, :
Proceedings 14th International Workshop on Verification of Infinite-State Systems, Infinity 2012, Paris, France, 27th August 2012. EPTCS 107, [contents]]]>https://dblp.org/rec/journals/corr/abs-1302-3105Sun, 01 Jan 2012 00:00:00 +0100 Ordered Counter-Abstraction.http://arxiv.org/abs/1204.0131:
Ordered Counter-Abstraction. CoRR abs/1204.0131 ()]]>https://dblp.org/rec/journals/corr/abs-1204-0131Sun, 01 Jan 2012 00:00:00 +0100 Automatic Verification of Directory-Based Consistency Protocols with Graph Constraints.https://doi.org/10.1142/S0129054111008416, , :
Automatic Verification of Directory-Based Consistency Protocols with Graph Constraints. Int. J. Found. Comput. Sci. 22(4): 761-782 ()]]>https://dblp.org/rec/journals/ijfcs/AbdullaDR11Sat, 01 Jan 2011 00:00:00 +0100 Invariant Synthesis for Programs Manipulating Lists with Unbounded Data.https://doi.org/10.1007/978-3-642-14295-6_8, , , , :
Invariant Synthesis for Programs Manipulating Lists with Unbounded Data. CAV : 72-88]]>https://dblp.org/rec/conf/cav/BouajjaniDERS10Fri, 01 Jan 2010 00:00:00 +0100 Constrained Monotonic Abstraction: A CEGAR for Parameterized Verification.https://doi.org/10.1007/978-3-642-15375-4_7, , , , , :
Constrained Monotonic Abstraction: A CEGAR for Parameterized Verification. CONCUR : 86-101]]>https://dblp.org/rec/conf/concur/AbdullaCDHHR10Fri, 01 Jan 2010 00:00:00 +0100 Proceedings 12th International Workshop on Verification of Infinite-State Systems, INFINITY 2010, Singapore, Singapore, 21st September 2010.https://doi.org/10.4204/EPTCS.39, :
Proceedings 12th International Workshop on Verification of Infinite-State Systems, INFINITY 2010, Singapore, Singapore, 21st September 2010. EPTCS 39, [contents]]]>https://dblp.org/rec/journals/corr/abs-1010-6112Fri, 01 Jan 2010 00:00:00 +0100 Approximated parameterized verification of infinite-state processes with global conditions.https://doi.org/10.1007/s10703-008-0062-9, , :
Approximated parameterized verification of infinite-state processes with global conditions. Formal Methods Syst. Des. 34(2): 126-156 ()]]>https://dblp.org/rec/journals/fmsd/AbdullaDR09Thu, 01 Jan 2009 00:00:00 +0100 Monotonic Abstraction: on Efficient Verification of Parameterized Systems.https://doi.org/10.1142/S0129054109006887, , , :
Monotonic Abstraction: on Efficient Verification of Parameterized Systems. Int. J. Found. Comput. Sci. 20(5): 779-801 ()]]>https://dblp.org/rec/journals/ijfcs/AbdullaDHR09Thu, 01 Jan 2009 00:00:00 +0100 Approximated Context-Sensitive Analysis for Parameterized Verification.https://doi.org/10.1007/978-3-642-02138-1_3, , :
Approximated Context-Sensitive Analysis for Parameterized Verification. FMOODS/FORTE : 41-56]]>https://dblp.org/rec/conf/forte/AbdullaDR09Thu, 01 Jan 2009 00:00:00 +0100 Automatic Verification of Directory-Based Consistency Protocols.https://doi.org/10.1007/978-3-642-04420-5_6, , :
Automatic Verification of Directory-Based Consistency Protocols. RP : 36-50]]>https://dblp.org/rec/conf/rp/AbdullaDR09Thu, 01 Jan 2009 00:00:00 +0100 Parameterized Systems: Generalizing and Simplifying Automatic Verification.https://nbn-resolving.org/urn:nbn:se:uu:diva-8587:
Parameterized Systems: Generalizing and Simplifying Automatic Verification. Uppsala University, Sweden, ]]>https://dblp.org/rec/phd/basesearch/Rezine08Tue, 01 Jan 2008 00:00:00 +0100 Monotonic Abstraction for Programs with Dynamic Memory Heaps.https://doi.org/10.1007/978-3-540-70545-1_33, , , , :
Monotonic Abstraction for Programs with Dynamic Memory Heaps. CAV : 341-354]]>https://dblp.org/rec/conf/cav/AbdullaBCHR08Tue, 01 Jan 2008 00:00:00 +0100 Parameterized Tree Systems.https://doi.org/10.1007/978-3-540-68855-6_5, , , , :
Parameterized Tree Systems. FORTE : 69-83]]>https://dblp.org/rec/conf/forte/AbdullaHDHR08Tue, 01 Jan 2008 00:00:00 +0100 Monotonic Abstraction in Action.https://doi.org/10.1007/978-3-540-85762-4_4, , :
Monotonic Abstraction in Action. ICTAC : 50-65]]>https://dblp.org/rec/conf/ictac/AbdullaDR08Tue, 01 Jan 2008 00:00:00 +0100 Handling Parameterized Systems with Non-atomic Global Conditions.https://doi.org/10.1007/978-3-540-78163-9_7, , , :
Handling Parameterized Systems with Non-atomic Global Conditions. VMCAI : 22-36]]>https://dblp.org/rec/conf/vmcai/AbdullaHDR08Tue, 01 Jan 2008 00:00:00 +0100 Monotonic Abstraction in Parameterized Verification.https://doi.org/10.1016/j.entcs.2008.12.027, , :
Monotonic Abstraction in Parameterized Verification. RP : 3-14]]>https://dblp.org/rec/journals/entcs/AbdullaDR08Tue, 01 Jan 2008 00:00:00 +0100 Shape Analysis via Monotonic Abstraction.http://drops.dagstuhl.de/opus/volltexte/2008/1559/, , , , , :
Shape Analysis via Monotonic Abstraction. Beyond the Finite: New Challenges in Verification and Semistructured Data ]]>https://dblp.org/rec/conf/dagstuhl/AbdullaBCHJR08Tue, 01 Jan 2008 00:00:00 +0100 Parameterized Verification of Infinite-State Processes with Global Conditions.https://doi.org/10.1007/978-3-540-73368-3_17, , :
Parameterized Verification of Infinite-State Processes with Global Conditions. CAV : 145-157]]>https://dblp.org/rec/conf/cav/AbdullaDR07Mon, 01 Jan 2007 00:00:00 +0100 Regular Model Checking Without Transducers (On Efficient Verification of Parameterized Systems).https://doi.org/10.1007/978-3-540-71209-1_56, , , :
Regular Model Checking Without Transducers (On Efficient Verification of Parameterized Systems). TACAS : 721-736]]>https://dblp.org/rec/conf/tacas/AbdullaDHR07Mon, 01 Jan 2007 00:00:00 +0100 Tree regular model checking: A simulation-based approach.https://doi.org/10.1016/j.jlap.2006.02.001, , , :
Tree regular model checking: A simulation-based approach. J. Log. Algebraic Methods Program. 69(1-2): 93-121 ()]]>https://dblp.org/rec/journals/jlp/AbdullaLdR06Sun, 01 Jan 2006 00:00:00 +0100 Proving Liveness by Backwards Reachability.https://doi.org/10.1007/11817949_7, , , :
Proving Liveness by Backwards Reachability. CONCUR : 95-109]]>https://dblp.org/rec/conf/concur/AbdullaJRS06Sun, 01 Jan 2006 00:00:00 +0100 Simulation-Based Iteration of Tree Transducers.https://doi.org/10.1007/978-3-540-31980-1_3, , , :
Simulation-Based Iteration of Tree Transducers. TACAS : 30-44]]>https://dblp.org/rec/conf/tacas/AbdullaLdR05Sat, 01 Jan 2005 00:00:00 +0100