default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDIEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 20
Volume 20, Number 1, January 2012
- Craig Schlottmann, David Abramson, Paul E. Hasler:
A MITE-Based Translinear FPAA. 1-9 - Craig Schlottmann, Csaba Petre, Paul E. Hasler:
A High-Level Simulink-Based Tool for FPAA Configuration. 10-18 - Hongbin Sun, Chuanyin Liu, Wei Xu, Jizhong Zhao, Nanning Zheng, Tong Zhang:
Using Magnetic RAM to Build Low-Power and Soft Error-Resilient L1 Cache. 19-28 - Afshin Nourivand, Asim J. Al-Khalili, Yvon Savaria:
Postsilicon Tuning of Standby Supply Voltage in SRAMs to Reduce Yield Losses Due to Parametric Data-Retention Failures. 29-41 - Maurice Meijer, José Pineda de Gyvez:
Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits. 42-51 - Kubilay Atasu
, Wayne Luk, Oskar Mencer, Can C. Özturan, Günhan Dündar:
FISH: Fast Instruction SyntHesis for Custom Processors. 52-65 - Jinwook Jang, Olivier Franza, Wayne P. Burleson:
Compact Expressions for Supply Noise Induced Period Jitter of Global Binary Clock Trees. 66-79 - Kun-Hung Tsai, Shen-Iuan Liu:
A 104-GHz Phase-Locked Loop Using a VCO at Second Pole Frequency. 80-88 - Wei Yao, Yiyu Shi, Lei He, Sudhakar Pamarti:
Worst-Case Estimation for Data-Dependent Timing Jitter and Amplitude Noise in High-Speed Differential Link. 89-97 - Zheng Li, Moustafa Mohamed, Xi Chen, Eric Dudley, Ke Meng, Li Shang, Alan Rolf Mickelson, Russ Joseph, Manish Vachharajani, Brian Schwartz, Yihe Sun:
Reliability Modeling and Management of Nanophotonic On-Chip Networks. 98-111 - Hassan Salmani, Mohammad Tehranipoor, Jim Plusquellic:
A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation Time. 112-125 - Geng-Ming Chiu, James Chien-Mo Li:
A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores. 126-134 - Mahdi Shabany, P. Glenn Gulak:
A 675 Mbps, 4 × 4 64-QAM K-Best MIMO Detector in 0.13 µm CMOS. 135-147 - Shih-Fu Liu, Pedro Reviriego, Juan Antonio Maestro:
Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications. 148-156 - Faiz-ul Hassan, Wim Vanderbauwhede, Fernando Rodríguez Salazar:
Impact of Random Dopant Fluctuations on the Timing Characteristics of Flip-Flops. 157-161 - Maurizio Costagliola, Davide De Caro, Antonio Girardi, Roberto Izzi, Niccolò Rinaldi, Marco Spirito, Paolo Spirito:
An Experimental Power-Lines Model for Digital ASICs Based on Transmission Lines. 162-166 - Tung-Hua Yeh, Sying-Jyan Wang:
Power-Aware High-Level Synthesis With Clock Skew Management. 167-171 - Irith Pomeranz, Sudhakar M. Reddy:
Resolution of Diagnosis Based on Transition Faults. 172-176 - Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis. 176-181 - Jisu Kim, Kyungho Ryu, Seung-Hyuk Kang, Seong-Ook Jung:
A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM). 181-186 - Xiaoxia Wu, Wei Zhao, Mark Nakamoto, Chandra Nimmagadda, Durodami Lisk, Sam Gu, Riko Radojcic, Matt Nowak, Yuan Xie:
Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs. 186-191 - Andrew B. Kahng, Bin Li, Li-Shiuan Peh, Kambiz Samadi:
ORION 2.0: A Power-Area Simulator for Interconnection Networks. 191-196
Volume 20, Number 2, February 2012
- Raghavendra Kulkarni, Jusung Kim, Hyung-Joon Jeon, Jianhong Xiao, José Silva-Martínez:
UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations. 197-210 - Thom Jefferson A. Eguia, Sheldon X.-D. Tan, Ruijing Shen, Duo Li, Eduardo H. Pacheco, Murli Tirumala, Lingli Wang:
General Parameterized Thermal Modeling for High-Performance Microprocessor Design. 211-224 - Jungseob Lee, Nam Sung Kim:
Analyzing Potential Throughput Improvement of Power- and Thermal-Constrained Multicore Processors by Exploiting DVFS and PCPG. 225-235 - Xiang Fu, Huawei Li, Xiaowei Li:
Testable Path Selection and Grouping for Faster Than At-Speed Testing. 236-247 - Sang Phill Park, Dongsoo Lee, Kaushik Roy:
Soft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product Code. 248-256 - Mohammad Abdullah Al Faruque, Thomas Ebi, Jörg Henkel:
AdNoC: Runtime Adaptive Network-on-Chip Architecture. 257-269 - Phi-Hung Pham, Jongsun Park, Phuong Mau, Chulwoo Kim:
Design and Implementation of Backtracking Wave-Pipeline Switch to Support Guaranteed Throughput in Network-on-Chip. 270-283 - Elio Consoli, Gaetano Palumbo, Melita Pennisi:
Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master-Slave Flip-Flops. 284-295 - Ning Chen, Zhiyuan Yan, Maximilien Gadouleau, Ying Wang, Bruce W. Suter:
Rank Metric Decoder Architectures for Random Linear Network Coding With Error Control. 296-309 - Younghoon Lee, Jungsoo Kim, Chong-Min Kyung:
Energy-Aware Video Encoding for Image Quality Improvement in Battery-Operated Surveillance Camera. 310-318 - Jaydeep P. Kulkarni, Kaushik Roy:
Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design. 319-332 - Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye:
Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits. 333-343 - Jim Le, Christopher Hanken, Martin Held, Michael S. Hagedorn, Kartikeya Mayaram, Terri S. Fiez:
Experimental Characterization and Analysis of an Asynchronous Approach for Reduction of Substrate Noise in Digital Circuitry. 344-356 - Antonis M. Paschalis, Ioannis Voyiatzis, Dimitris Gizopoulos:
Accumulator Based 3-Weight Pattern Generation. 357-361 - Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu:
Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme. 361-366 - Yu-Chi Tsao, Ken Choi:
Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm. 366-371 - B. Ramkumar, Harish M. Kittur:
Low-Power and Area-Efficient Carry Select Adder. 371-375 - Manthena Vamshi Krishna, Manh Anh Do, Chirn Chye Boon, Kiat Seng Yeo:
A Low-Power Single-Phase Clock Multiband Flexible Divider. 376-380 - Ehsan Pakbaznia, Massoud Pedram:
Design of a Tri-Modal Multi-Threshold CMOS Switch With Application to Data Retentive Power Gating. 380-385 - Chung-Yi Li, Yuan-Ho Chen, Tsin-Yuan Chang, Lih-Yuan Deng, Kiwing To:
Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG. 385-389
Volume 20, Number 3, March 2012
- Jung-Won Han, Kwisung Yoo, Dongmyung Lee, Kangyeob Park, Wonseok Oh, Sung Min Park:
A Low-Power Gigabit CMOS Limiting Amplifier Using Negative Impedance Compensation and Its Application. 393-399 - Muhammad Khurram, S. M. Rezaul Hasan:
A 3-5 GHz Current-Reuse gm-Boosted CG LNA for Ultrawideband in 130 nm CMOS. 400-409 - Stelios Neophytou, Maria K. Michael:
Test Pattern Generation of Relaxed n-Detect Test Sets. 410-423 - Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu:
Test Pattern Generation for Multiple Aggressor Crosstalk Effects Considering Gate Leakage Loading in Presence of Gate Delays. 424-436 - José Luis Núñez-Yáñez, Atukem Nabina, Eddie Hung, George Vafiadis:
Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding. 437-448 - M. Anwar Hasan, Ashkan Hosseinzadeh Namin, Christophe Nègre:
Toeplitz Matrix Approach for Binary Field Multiplication Using Quadrinomials. 449-458 - Ke-Ren Dai, Wen-Hao Liu, Yih-Lang Li:
NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing. 459-472 - Jai-Ming Lin, Zhi-Xiong Hung:
SKB-Tree: A Fixed-Outline Driven Representation for Modern Floorplanning Problems. 473-484 - Iris Hui-Ru Jiang, Hua-Yu Chang:
ECOS: Stable Matching Based Metal-Only ECO Synthesis. 485-497 - Jiying Xue, Yangdong Deng, Zuochang Ye, Hongrui Wang, Liu Yang, Zhiping Yu:
A Framework for Layout-Dependent STI Stress Analysis and Stress-Aware Circuit Optimization. 498-511 - Koushik Chakraborty, Sanghamitra Roy:
Stack Aware Threshold Voltage Assignment in 3-D Multicore Designs. 512-522 - Atanu Chattopadhyay, Zeljko Zilic:
Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution Networks. 523-536 - Jason Helge Anderson, Qiang Wang, Chirag Ravishankar:
Raising FPGA Logic Density Through Synthesis-Inspired Architecture. 537-550 - Xuan Guan, Yunsi Fei, Hai Lin:
Hierarchical Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT Processing. 551-563 - Sebastian Hoyos, Cheongyuen W. Tsang, Johan P. Vanderhaegen, Yun Chiu, Yasutoshi Aibara, Haideh Khorramabadi, Borivoje Nikolic:
A 15 MHz to 600 MHz, 20 mW, 0.38 mm2 Split-Control, Fast Coarse Locking Digital DLL in 0.13 µ m CMOS. 564-568 - Francisco Garcia-Herrero, María José Canet, Javier Valls, Pramod Kumar Meher:
High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes. 568-573 - Amine Dehbaoui, Victor Lomné, Thomas Ordas, Lionel Torres, Michel Robert, Philippe Maurine:
Enhancing Electromagnetic Analysis Using Magnitude Squared Incoherence. 573-577
Volume 20, Number 4, April 2012
- Iris Hui-Ru Jiang, Hua-Yu Chang, Chih-Long Chang:
WiT: Optimal Wiring Topology for Electromigration Avoidance. 581-592 - Insup Shin, Seungwhun Paik, Dongwan Shin, Youngsoo Shin:
HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures. 593-604 - Mingoo Seok, Scott Hanson, David T. Blaauw, Dennis Sylvester:
Sleep Mode Analysis and Optimization With Minimal-Sized Power Gating Switch for Ultra-Low ${V}_{\rm dd}$ Operation. 605-615 - Taniya Siddiqua, Sudhanva Gurumurthi:
Enhancing NBTI Recovery in SRAM Arrays Through Recovery Boosting. 616-629 - Avesta Sasan, Kiarash Amiri, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi:
Variation Trained Drowsy Cache (VTD-Cache): A History Trained Variation Aware Drowsy Cache for Fine Grain Voltage Scaling. 630-642 - Shuai Wang, Jie S. Hu, Sotirios G. Ziavras:
Replicating Tag Entries for Reliability Enhancement in Cache Tag Arrays. 643-654 - Yuan-Ho Chen, Tsin-Yuan Chang:
A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy. 655-664 - Chang-Hsin Cheng, Yu Liu, Chun-Lung Hsu:
Design of an Error Detection and Data Recovery Architecture for Motion Estimation Testing Applications. 665-672 - Ta-Wen Kuan, Jhing-Fa Wang, Jia-Ching Wang, Po-Chuan Lin, Gaung-Hui Gu:
VLSI Design of an SVM Learning Core on Sequential Minimal Optimization Algorithm. 673-683 - Mame Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre:
Loop Acceleration Exploration for ASIP Architecture. 684-696 - Kai Liu, Evgeniy Belyaev, Jie Guo:
VLSI Architecture of Arithmetic Coder Used in SPIHT. 697-710 - Ang-Chih Hsieh, TingTing Hwang:
TSV Redundancy: Architecture and Design Issues in 3-D IC. 711-722 - Zhaobo Zhang, Zhanglei Wang, Xinli Gu, Krishnendu Chakrabarty:
Physical-Defect Modeling and Optimization for Fault-Insertion Test. 723-736 - Moo-young Kim, Hokyu Lee, Chulwoo Kim:
PVT Variation Tolerant Current Source With On-Chip Digital Self-Calibration. 737-741 - Hailong Jiao, Volkan Kursun:
Threshold Voltage Tuning for Faster Activation With Lower Noise in Tri-Mode MTCMOS Circuits. 741-745 - Shao-Chang Huang, Ke-Horng Chen, Weiyao Lin, Zon-Lon Lee, Kun-Wei Chang, Erica Hsu, Wenson Lee, Lin-Fwu Chen, Chris Chun-Hung Lu:
Embedded I/O PAD Circuit Design for OTP Memory Power-Switch Functionality. 746-750 - Golnar Khodabandehloo, Mitra Mirhassani, Majid Ahmadi:
Analog Implementation of a Novel Resistive-Type Sigmoidal Neuron. 750-754 - Jinjin He, Huaping Liu, Zhongfeng Wang, Xinming Huang, Kai Zhang:
High-Speed Low-Power Viterbi Decoder Design for TCM Decoders. 755-759 - Junhui Gu, Jianhui Wu, Danhong Gu, Meng Zhang, Longxing Shi:
All-Digital Wide Range Precharge Logic 50% Duty Cycle Corrector. 760-764 - Sang-Hyun Cho, Chang-Kyo Lee, Sang-Gug Lee, Seung-Tak Ryu:
A Two-Channel Asynchronous SAR ADC With Metastable-Then-Set Algorithm. 765-769 - Hassan Mostafa, Mohab Anis, Mohamed I. Elmasry:
On-Chip Process Variations Compensation Using an Analog Adaptive Body Bias (A-ABB). 770-774
Volume 20, Number 5, May 2012
- Songjun Pan, Yu Hu, Xiaowei Li:
IVF: Characterizing the Vulnerability of Microprocessor Structures to Intermittent Faults. 777-790 - W. Paul Griffin, Anand Raghunathan, Kaushik Roy:
CLIP: Circuit Level IC Protection Through Direct Injection of Process Variations. 791-803 - Kentaroh Katoh, Kazuteru Namba, Hideo Ito:
An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection. 804-817 - Anson H. T. Tse, David B. Thomas, Wayne Luk:
Design Exploration of Quadrature Methods in Option Pricing. 818-826 - Miroslav Knezevic, Kazuyuki Kobayashi, Jun Ikegami, Shin'ichiro Matsuo, Akashi Satoh, Ünal Koçabas, Junfeng Fan, Toshihiro Katashita, Takeshi Sugawara, Kazuo Sakiyama, Ingrid Verbauwhede, Kazuo Ohta, Naofumi Homma, Takafumi Aoki:
Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates. 827-840 - Chieh-Jen Cheng, Chao-Ching Wang, Wei-Chun Ku, Tien-Fu Chen, Jinn-Shyan Wang:
A Scalable High-Performance Virus Detection Processor Against a Large Pattern Set for Embedded Network Security. 841-854 - Fahad Ahmed, Linda Milor:
Analysis and On-Chip Monitoring of Gate Oxide Breakdown in SRAM Cells. 855-864 - Boyuan Yan, Sheldon X.-D. Tan, Lingfei Zhou, Jie Chen, Ruijing Shen:
Decentralized and Passive Model Order Reduction of Linear Networks With Massive Ports. 865-877 - Tobias Strauch:
Single Cycle Access Structure for Logic Test. 878-891 - Nandish Ashutosh Mehta, Bharadwaj Amrutur:
Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor. 892-901 - Weixun Wang, Prabhat Mishra:
System-Wide Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Multitasking Systems. 902-910 - Rahul Rithe, Sharon Chou, Jie Gu, Alice Wang, Satyendra Datla, Gordon Gammie, Dennis Buss, Anantha P. Chandrakasan:
The Effect of Random Dopant Fluctuations on Logic Timing at Low Voltage. 911-924 - Saumya Chandra, Anand Raghunathan, Sujit Dey:
Variation-Aware Voltage Level Selection. 925-936 - Cheng-Wen Wei, Sheng-Jie Su, Tian-Sheuan Chang, Shyh-Jye Jou:
Sub µW Noise Reduction for CIC Hearing Aids. 937-947 - Tai-You Lu, Wei-Zen Chen:
A 3-10 GHz, 14 Bands CMOS Frequency Synthesizer With Spurs Reduction for MB-OFDM UWB System. 948-958 - Terng-Yin Hsu, Shau-Yu Cheng:
Low-Complexity Sequential Searcher for Robust Symbol Synchronization in OFDM Systems. 959-963 - Won-Young Lee, Lee-Sup Kim:
An Adaptive Equalizer With the Capacitance Multiplication for DisplayPort Main Link in 0.18-µm CMOS. 964-968 - Jaehyouk Choi, Woonyun Kim, Kyutae Lim:
A Spur Suppression Technique Using an Edge-Interpolator for a Charge-Pump PLL. 969-973
Volume 20, Number 6, June 2012
- Jerry C. Kao, Wei-Hsiang Ma, Visvesh S. Sathe, Marios C. Papaefthymiou:
Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic. 977-988 - Wei-Chih Hsieh, Wei Hwang:
All Digital Linear Voltage Regulator for Super- to Near-Threshold Operation. 989-1001 - Jianchao Lu, Ying Teng, Baris Taskin:
A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs. 1002-1011 - Wei Fei, Hao Yu, Wei Zhang, Kiat Seng Yeo:
Design Exploration of Hybrid CMOS and Memristor Circuit by New Modified Nodal Analysis. 1012-1025 - Irith Pomeranz:
Gradual Diagnostic Test Generation and Observation Point Insertion Based on the Structural Distance Between Indistinguished Fault Pairs. 1026-1035 - Zhen Wang, Mark G. Karpovsky, Ajay Joshi:
Secure Multipliers Resilient to Strong Fault-Injection Attacks Using Multilinear Arithmetic Codes. 1036-1048 - Sheng Wei, Miodrag Potkonjak:
Scalable Hardware Trojan Diagnosis. 1049-1057 - Francisco Barranco, Matteo Tomasi, Javier Díaz, Mauricio Vanegas, Eduardo Ros:
Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA. 1058-1067 - Manohar Ayinala, Michael J. Brown, Keshab K. Parhi:
Pipelined Parallel FFT Architectures via Folding Transformation. 1068-1081 - Seok-Hoon Kim, Sung-Eui Yoon, Sang-Hye Chung, Young-Jun Kim, Hong-Yun Kim, Kyusik Chung, Lee-Sup Kim:
A Mobile 3-D Display Processor With A Bandwidth-Saving Subdivider. 1082-1093 - Duo Liu, Yi Wang, Zhiwei Qin, Zili Shao, Yong Guan:
A Space Reuse Strategy for Flash Translation Layers in SLC NAND Flash Memory Storage Systems. 1094-1107 - Alejandro Valero, Julio Sahuquillo, Vicente Lorente, Salvador Petit, Pedro López, José Duato:
Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches. 1108-1117 - Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici:
Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment. 1118-1131 - Yang Zhao, Krishnendu Chakrabarty, Ryan Sturmer, Vamsee K. Pamula:
Optimization Techniques for the Synchronization of Concurrent Fluidic Operations in Pin-Constrained Digital Microfluidic Biochips. 1132-1145 - Sampo Tuuna, Ethiopia Nigussie, Jouni Isoaho, Hannu Tenhunen:
Modeling of Energy Dissipation in RLC Current-Mode Signaling. 1146-1151 - Ming Ming Wong, M. L. Dennis Wong, Asoke K. Nandi, Ismat Hijazin:
Construction of Optimum Composite Field Architecture for Compact High-Throughput AES S-Boxes. 1151-1155 - Irith Pomeranz:
Multi-Pattern $n$-Detection Stuck-At Test Sets for Delay Defect Coverage. 1156-1160
Volume 20, Number 7, July 2012
- Chixiang Ma, Hao Cao, Ping Lin:
A Low-Power Low-Cost Design of Primary Synchronization Signal Detection. 1161-1166 - Yanqi Zheng, Hua Chen, Ka Nang Leung:
A Fast-Response Pseudo-PWM Buck Converter With PLL-Based Hysteresis Control. 1167-1174 - Hang Yu, Lin Zhong, Ashutosh Sabharwal:
Power Management of MIMO Network Interfaces on Mobile Systems. 1175-1186 - Min Bao, Alexandru Andrei, Petru Eles, Zebo Peng:
Temperature-Aware Idle Time Distribution for Leakage Energy Optimization. 1187-1200 - Chien-Yu Hsieh, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang:
Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs. 1201-1210 - Randy W. Mann, Terry B. Hook, Phung T. Nguyen, Benton H. Calhoun:
Nonrandom Device Mismatch Considerations in Nanoscale SRAM. 1211-1220 - Zhen Wang, Mark G. Karpovsky, Ajay Joshi:
Nonlinear Multi-Error Correction Codes for Reliable MLC nand Flash Memories. 1221-1234 - Yang Sun, Joseph R. Cavallaro:
High-Throughput Soft-Output MIMO Detector Based on Path-Preserving Trellis-Search Algorithm. 1235-1247 - Seokjoong Hwang, Youngsun Han, Seon Wook Kim, Jongsun Park, Byung Gueon Min:
Resource Efficient Implementation of Low Power MB-OFDM PHY Baseband Modem With Highly Parallel Architecture. 1248-1261 - Nuno Sebastião, Nuno Roma, Paulo F. Flores:
Integrated Hardware Architecture for Efficient Computation of the $n$-Best Bio-Sequence Local Alignments in Embedded Platforms. 1262-1275 - Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn:
Hardware Implementation of Nakagami and Weibull Variate Generators. 1276-1284 - Kiichi Niitsu, Shusuke Kawai, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
A 65fJ/b Inter-Chip Inductive-Coupling Data Transceivers Using Charge-Recycling Technique for Low-Power Inter-Chip Communication in 3-D System Integration. 1285-1294 - Chi Wai Yu, Alastair M. Smith, Wayne Luk, Philip Heng Wai Leong, Steven J. E. Wilton:
Optimizing Floating Point Units in Hybrid FPGAs. 1295-1303 - Qiaoyan Yu, Paul Ampadu:
Dual-Layer Adaptive Error Control for Network-on-Chip Links. 1304-1317 - Xinmiao Zhang, Yingquan Wu, Jiangli Zhu, Yu Zheng:
Novel Interpolation and Polynomial Selection for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding. 1318-1322 - Kavallur Gopi Smitha, A. Prasad Vinod:
A Multi-Resolution Fast Filter Bank for Spectrum Sensing in Military Radio Receivers. 1323-1327 - Sohan Purohit, Martin Margala:
Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance. 1327-1331 - Kalyan Bhattacharyya, Ted H. Szymanski:
Temperature Characteristics and Analysis of Monolithic Microwave CMOS Distributed Oscillators With ${G}_{m}$-Varied Gain Cells and Folded Coplanar Interconnects. 1332-1336 - Kangmin Hu, Larry Wu, Patrick Yin Chiang:
A Comparative Study of 20-Gb/s NRZ and Duobinary Signaling Using Statistical Analysis. 1336-1341 - Azzurra Pulimeno, Mariagrazia Graziano, Gianluca Piccinini:
UDSM Trends Comparison: From Technology Roadmap to UltraSparc Niagara2. 1341-1346 - Li Li, Bo Yuan, Zhongfeng Wang, Jin Sha, Hongbing Pan, Weishan Zheng:
Unified Architecture for Reed-Solomon Decoder Combined With Burst-Error Correction. 1346-1350 - Fei Hong, Aviral Shrivastava, Jongeun Lee:
Return Data Interleaving for Multi-Channel Embedded CMPs Systems. 1351-1354
Volume 20, Number 8, August 2012
- Horng-Yuan Shih, Chih-Wei Wang:
A Highly-Integrated 3-8 GHz Ultra-Wideband RF Transmitter With Digital-Assisted Carrier Leakage Calibration and Automatic Transmit Power Control. 1357-1367 - Tae-Kwang Jang, Jaewook Kim, Young-Gyu Yoon, SeongHwan Cho:
A Highly-Digital VCO-Based Analog-to-Digital Converter Using Phase Interpolator and Digital Calibration. 1368-1372 - Jee Khoi Yin, Pak Kwong Chan:
Jitter Analysis of Polyphase Filter-Based Multiphase Clock in Frequency Multiplier. 1373-1382 - Lerong Cheng, Fang Gong, Wenyao Xu, Jinjun Xiong, Lei He, Majid Sarrafzadeh:
Fourier Series Approximation for Max Operation in Non-Gaussian and Quadratic Statistical Static Timing Analysis. 1383-1391 - Sebastian Herbert, Siddharth Garg, Diana Marculescu:
Exploiting Process Variability in Voltage/Frequency Control. 1392-1404 - Xiaoxiao Wang, Mohammad Tehranipoor, Saji George, Dat Tran, LeRoy Winemberg:
Design and Analysis of a Delay Sensor Applicable to Process/Environmental Variations and Aging Measurements. 1405-1418 - Zhong-Ho Chen, Alvin Wen-Yu Su, Ming-Ting Sun:
Resource-Efficient FPGA Architecture and Implementation of Hough Transform. 1419-1428 - Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose:
Portable, Flexible, and Scalable Soft Vector Processors. 1429-1442 - Yunlei Li, Jin Liu, Hoi Lee:
Ground Switching Load Modulation With Ground Isolation for Passive HF RFID Transponders. 1443-1452 - Reza Azarderakhsh, Arash Reyhani-Masoleh:
Efficient FPGA Implementations of Point Multiplication on Binary Edwards and Generalized Hessian Curves Using Gaussian Normal Basis. 1453-1466 - Davide Baccarin, David Esseni, Massimo Alioto:
Mixed FBB/RBB: A Novel Low-Leakage Technique for FinFET Forced Stacks. 1467-1472 - Shaobo Liu, Jun Lu, Qing Wu, Qinru Qiu:
Harvesting-Aware Power Management for Real-Time Systems With Renewable Energy. 1473-1486 - Felice Crupi, Massimo Alioto, Jacopo Franco, Paolo Magnone, Ben Kaczer, Guido Groeseneken, Jérôme Mitard, Liesbeth Witters, Thomas Y. Hoffmann:
Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling. 1487-1495 - Ou He, Sheqin Dong, Wooyoung Jang, Jinian Bian, David Z. Pan:
UNISM: Unified Scheduling and Mapping for General Networks on Chip. 1496-1509 - Darío Suárez Gracia, Giorgos Dimitrakopoulos, Teresa Monreal Arnal, Manolis Katevenis, Víctor Viñals Yúfera:
LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors. 1510-1523 - Young-Jae Min, Chan-Hui Jeong, Kyu-Young Kim, Won Ho Choi, Jong-Pil Son, Chulwoo Kim, Soo-Won Kim:
A 0.31-1 GHz Fast-Corrected Duty-Cycle Corrector With Successive Approximation Register for DDR DRAM Applications. 1524-1528 - Vinayak Honkote, Baris Taskin:
ZeROA: Zero Clock Skew Rotary Oscillatory Array. 1528-1532 - Joonho Kong, Yan Pan, Serkan Ozdemir, Anitha Mohan, Gokhan Memik, Sung Woo Chung:
Fine-Grain Voltage Tuned Cache Architecture for Yield Management Under Process Variations. 1532-1536 - Chung-An Shen, Ahmed M. Eltawil, Khaled N. Salama, Sudip Mondal:
A Best-First Soft/Hard Decision Tree Searching MIMO Decoder for a 4 × 4 64-QAM System. 1537-1541 - Supriya Aggarwal, Pramod Kumar Meher, Kavita Khare:
Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection. 1542-1546 - Seyed Ebrahim Esmaeili, Asim J. Al-Khalili, Glenn E. R. Cowan:
Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks. 1547-1551
Volume 20, Number 9, September 2012
- Yongtao Geng, Huan Zou, Chaojiang Li, Jiwei Sun, Haibo Wang, Pingshan Wang:
Short Pulse Generation With On-Chip Pulse-Forming Lines. 1553-1564 - Songwei Pei, Huawei Li, Xiaowei Li:
A High-Precision On-Chip Path Delay Measurement Architecture. 1565-1577 - Amir Moradi, Mario Kirschbaum, Thomas Eisenbarth, Christof Paar:
Masked Dual-Rail Precharge Logic Encounters State-of-the-Art Power Analysis Methods. 1578-1589 - Dongwan Ha, Kyoungho Woo, Scott E. Meninger, Thucydides Xanthopoulos, Ethan Crain, Donhee Ham:
Time-Domain CMOS Temperature Sensors With Dual Delay-Locked Loops for Microprocessor Thermal Monitoring. 1590-1601 - Shreyas Sen, Shyam Kumar Devarakond, Abhijit Chatterjee:
Phase Distortion to Amplitude Conversion-Based Low-Cost Measurement of AM-AM and AM-PM Effects in RF Power Amplifiers. 1602-1614 - Chien-Ying Yu, Jui-Yuan Yu, Chen-Yi Lee:
A Low Voltage All-Digital On-Chip Oscillator Using Relative Reference Modeling. 1615-1620 - Li Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. Mak:
Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint. 1621-1633 - Palkesh Jain, Ankit Jain:
Accurate Current Estimation for Interconnect Reliability Analysis. 1634-1644 - Prashant Singh, Eric Karl, David T. Blaauw, Dennis Sylvester:
Compact Degradation Sensors for Monitoring NBTI and Oxide Degradation. 1645-1655 - Cheng-Ta Chiang, Chih-Hsien Wang, Chia-Yu Wu:
A CMOS MEMS Audio Transducer Implemented by Silicon Condenser Microphone With Analog Front-End Circuits of Audio Codec. 1656-1667 - Weirong Jiang, Viktor K. Prasanna:
Scalable Packet Classification on FPGA. 1668-1680 - Hiva Hedayati, Bertan Bakkaloglu:
A 3 GHz Wideband Σ Δ Fractional-N Synthesizer With Switched-RC Sample-and-Hold PFD. 1681-1690 - Young-Jun Kim, Hyo-Eun Kim, Seok-Hoon Kim, Jun-Seok Park, Seungwook Paek, Lee-Sup Kim:
Homogeneous Stream Processors With Embedded Special Function Units for High-Utilization Programmable Shaders. 1691-1704 - Guiqiang Dong, Yangyang Pan, Ningde Xie, Chandra Varanasi, Tong Zhang:
Estimating Information-Theoretical nand Flash Memory Storage Capacity and its Implication to Memory System Design Space Exploration. 1705-1714 - Hao-Yu Yang, Chi-Min Chang, Mango Chia-Tso Chao, Rei-Fu Huang, Shih-Chin Lin:
Testing Methodology of Embedded DRAMs. 1715-1728 - Fang Gong, Hao Yu, Lingli Wang, Lei He:
A Parallel and Incremental Extraction of Variational Capacitance With Stochastic Geometric Moments. 1729-1737 - Yin-Tsung Hwang, Jin-Fa Lin:
Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique. 1738-1742 - Meng-Hung Shen, Po-Chiun Huang:
A Low Cost Calibrated DAC for High-Resolution Video Display System. 1743-1747
Volume 20, Number 10, 2012
- Debasri Saha, Susmita Sur-Kolay:
Secure Public Verification of IP Marks in FPGA Design Through a Zero-Knowledge Protocol. 1749-1757 - Yang Ge, Qinru Qiu, Qing Wu:
A Multi-Agent Framework for Thermal Aware Task Migration in Many-Core Systems. 1758-1771 - Shmuel Wimer, Israel Koren:
The Optimal Fan-Out of Clock Network for Power Minimization by Adaptive Gating. 1772-1780 - Yu-Huei Lee, Shao-Chang Huang, Shih-Wei Wang, Ke-Horng Chen:
Fast Transient (FT) Technique With Adaptive Phase Margin (APM) for Current Mode DC-DC Buck Converters. 1781-1793 - Kian Haghdad, Mohab Anis:
Power Yield Analysis Under Process and Temperature Variations. 1794-1803 - Stefan Erb, Wolfgang Pribyl:
Design Specification for BER Analysis Methods Using Built-In Jitter Measurements. 1804-1817 - Kuo-Hsing Cheng, Kai-Wei Hong, Chi-Fa Hsu, Bo-Qian Jiang:
An All-Digital Clock Synchronization Buffer With One Cycle Dynamic Synchronizing. 1818-1827 - Mingyu Wang, Hao Min:
Applying Effective Dynamic Frequency Scaling Method in Contactless Smart Card. 1828-1834 - Abhilash Goyal, Madhavan Swaminathan, Abhijit Chatterjee, Duane C. Howard, John D. Cressler:
A New Self-Healing Methodology for RF Amplifier Circuits Based on Oscillation Principles. 1835-1848 - Qi Zhang, Roger F. Woods, Alan Marshall:
An On-Demand Queue Management Architecture for a Programmable Traffic Manager. 1849-1862 - Ang-Chih Hsieh, TingTing Hwang:
Run-Time Reconfiguration of Expandable Cache for Embedded Systems. 1863-1875 - Xin Zhang, Koichi Ishida, Hiroshi Fuketa, Makoto Takamiya, Takayasu Sakurai:
On-Chip Measurement System for Within-Die Delay Variation of Individual Standard Cells in 65-nm CMOS. 1876-1880 - Biswajit Maity, Pradip Mandal:
A High Performance Switched Capacitor-Based DC-DC Buck Converter Suitable for Embedded Power Management Applications. 1880-1885 - Nam Sung Kim, Abhishek A. Sinkar, Jun Seomun, Youngsoo Shin:
Maximizing Frequency and Yield of Power-Constrained Designs Using Programmable Power-Gating. 1885-1890 - Hongxia Fang, Krishnendu Chakrabarty, Abhijit Jas, Srinivas Patil, Chandra Tirumurti:
Functional Test-Sequence Grading at Register-Transfer Level. 1890-1894 - Irith Pomeranz:
Generation of Mixed Test Sets for Transition Faults. 1895-1899 - Madhu Mutyam:
Fibonacci Codes for Crosstalk Avoidance. 1899-1903 - Young In Cho, Nam Su Chang, Chang Han Kim, Young-Ho Park, Seokhie Hong:
New Bit Parallel Multiplier With Low Space Complexity for All Irreducible Trinomials Over GF(2n). 1903-1908 - Shun-Hsun Yang, Yu-Jen Huang, Jin-Fu Li:
A Low-Power Ternary Content Addressable Memory With Pai-Sigma Matchlines. 1909-1913 - Jayanand Asok Kumar, Shobha Vasudevan:
Formal Performance Analysis for Faulty MIMO Hardware. 1914-1918 - Kangwoo Park, In-Cheol Park:
Low-Complexity Tone Reservation for PAPR Reduction in OFDM Communication Systems. 1919-1923 - I-Chyn Wey, Chun-Chien Wang:
Low-Error and Hardware-Efficient Fixed-Width Multiplier by Using the Dual-Group Minor Input Correction Vector to Lower Input Correction Vector Compensation Error. 1923-1928
Volume 20, Number 11, 2012
- Chingwei Yeh, Yuan-Chang Chen, Jinn-Shyan Wang:
Towards Process Variation-Aware Power Gating. 1929-1937 - Xinmiao Zhang, Fang Cai, Shu Lin:
Low-Complexity Reliability-Based Message-Passing Decoder Architectures for Non-Binary LDPC Codes. 1938-1950 - Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara:
A Failure Prediction Strategy for Transistor Aging. 1951-1959 - Jianxin Fang, Sachin S. Sapatnekar:
Scalable Methods for Analyzing the Circuit Failure Probability Due to Gate Oxide Breakdown. 1960-1973 - Stuart N. Wooters, Adam C. Cabe, Zhenyu Qi, Jiajing Wang, Randy W. Mann, Benton H. Calhoun, Mircea R. Stan, Travis N. Blalock:
Tracking On-Chip Age Using Distributed, Embedded Sensors. 1974-1985 - Aashish Pant, Puneet Gupta, Mihaela van der Schaar:
AppAdapt: Opportunistic Application Adaptation in Presence of Hardware Variation. 1986-1996 - Marcel Gort, Flavio M. de Paula, Johnny J. W. Kuan, Tor M. Aamodt, Alan J. Hu, Steven J. E. Wilton, Jin Yang:
Formal-Analysis-Based Trace Computation for Post-Silicon Debug. 1997-2010 - Suknam Kwon, Sungjoo Yoo, Sunggu Lee, Jinpyo Park:
Optimizing Video Application Design for Phase-Change RAM-Based Main Memory. 2011-2019 - Zhenyu Sun, Hai Li, Yiran Chen, Xiaobin Wang:
Voltage Driven Nondestructive Self-Reference Sensing Scheme of Spin-Transfer Torque Memory. 2020-2030 - P. Aubertin, J. M. Pierre Langlois, Yvon Savaria:
Real-Time Computation of Local Neighborhood Functions in Application-Specific Instruction-Set Processors. 2031-2043 - Kyungho Ryu, Jisu Kim, Jiwan Jung, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung:
A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention Flip-Flop. 2044-2053 - Sang Hyun Lee, Sriram Vishwanath:
Boolean Functions Over Nano-Fabrics: Improving Resilience Through Coding. 2054-2065 - Michael B. Healy, Sung Kyu Lim:
Distributed TSV Topology for 3-D Power-Supply Networks. 2066-2079 - Rohit Sunkam Ramanujam, Bill Lin:
Randomized Partially-Minimal Routing: Near-Optimal Oblivious Routing for 3-D Mesh Networks. 2080-2093 - Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham:
Fast Power- and Slew-Aware Gated Clock Tree Synthesis. 2094-2103 - Saket Gupta, Sachin S. Sapatnekar:
Compact Current Source Models for Timing Analysis Under Temperature and Body Bias Variations. 2104-2117 - Weiguo Tang, Jie Huang, Lei Wang, Shengli Zhou:
A Nonbinary LDPC Decoder Architecture With Adaptive Message Control. 2118-2122 - Yu-Jen Huang, Jin-Fu Li:
Low-Cost Self-Test Techniques for Small RAMs in SOCs Using Enhanced IEEE 1500 Test Wrappers. 2123-2127 - Marco Bucci, Luca Giancane, Raimondo Luzzi, Alessandro Trifiletti:
A Flip-Flop for the DPA Resistant Three-Phase Dual-Rail Pre-Charge Logic Family. 2128-2132 - Erick Amador, Raymond Knopp, Renaud Pacalet, Vincent Rezard:
Dynamic Power Management for the Iterative Decoding of Turbo Codes. 2133-2137 - Irith Pomeranz:
Non-Uniform Coverage by n -Detection Test Sets. 2138-2142 - Xiaoming Chen, Yu Wang, Yu Cao, Yuchun Ma, Huazhong Yang:
Variation-Aware Supply Voltage Assignment for Simultaneous Power and Aging Optimization. 2143-2147 - Wei Wu, Dinesh Somasekhar, Shih-Lien Lu:
Direct Compare of Information Coded With Error-Correcting Codes. 2147-2151 - Ting-Jung Lin, Wei Zhang, Niraj K. Jha:
SRAM-Based NATURE: A Dynamically Reconfigurable FPGA Based on 10T Low-Power SRAMs. 2151-2156
Volume 20, Number 12, 2012
- Songwei Pei, Huawei Li, Xiaowei Li:
Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume. 2157-2169 - Mingjing Chen, Alex Orailoglu:
Scan Power Reduction for Linear Test Compression Schemes Through Seed Selection. 2170-2183 - Hui-Hsiang Tung, Rung-Bin Lin, Mei-Chen Li, Tsung-Han Heish:
Standard Cell Like Via-Configurable Logic Blocks for Structured ASIC in an Industrial Design Flow. 2184-2197 - Haile Yu, Philip Heng Wai Leong, Qiang Xu:
An FPGA Chip Identification Generator Using Configurable Ring Oscillators. 2198-2207 - Matteo Tomasi, Mauricio Vanegas, Francisco Barranco, Javier Díaz, Eduardo Ros:
Real-Time Architecture for a Robust Multi-Scale Stereo Engine on FPGA. 2208-2219 - Reza Hashemian:
Application of Fixator-Norator Pairs in Designing Active Loads and Current Mirrors in Analog Integrated Circuits. 2220-2231 - Shoushun Chen, Wei Tang, Xiangyu Zhang, Eugenio Culurciello:
A 64 ˟ 64 Pixels UWB Wireless Temporal-Difference Digital Image Sensor. 2232-2240 - Rimesh M. Joshi, Arjuna Madanayake, Jithra Adikari, Leonard T. Bruton:
Synthesis and Array Processor Realization of a 2-D IIR Beam Filter for Wireless Applications. 2241-2254 - Fu-Wei Chen, Shih-Liang Chen, Yung-Sheng Lin, TingTing Hwang:
A Physical-Location-Aware X-Bit Redistribution for Maximum IR-Drop Reduction. 2255-2264 - Ethiopia Nigussie, Sampo Tuuna, Juha Plosila, Jouni Isoaho, Hannu Tenhunen:
Semi-Serial On-Chip Link Implementation for Energy Efficiency and High Throughput. 2265-2277 - Nicholas Axelos, Kiamal Z. Pekmestzi, Dimitris Gizopoulos:
Efficient Memory Repair Using Cache-Based Redundancy. 2278-2288 - Siddharth Garg, Diana Marculescu:
System-Level Leakage Variability Mitigation for MPSoC Platforms Using Body-Bias Islands. 2289-2301 - Chengen Yang, Yunus Emre, Chaitali Chakrabarti:
Product Code Schemes for Error Correction in MLC NAND Flash Memories. 2302-2314 - Sokehwan Kim, Hyunho Chu, Isaak Yang, Sanghoon Hong, Sung Hoon Jung, Kwang-Hyun Cho:
A Hierarchical Self-Repairing Architecture for Fast Fault Recovery of Digital Systems Inspired From Paralogous Gene Regulatory Circuits. 2315-2328 - Tse-Wei Chen, Yu-Chi Su, Keng-Yen Huang, Yi-Min Tsai, Shao-Yi Chien, Liang-Gee Chen:
Visual Vocabulary Processor Based on Binary Tree Architecture for Real-Time Object Recognition in Full-HD Resolution. 2329-2332 - Nam Sung Kim, Stark C. Draper, Shi-Ting Zhou, Sumeet Katariya, Hamid Reza Ghasemi, Taejoon Park:
Analyzing the Impact of Joint Optimization of Cell Size, Redundancy, and ECC on Low-Voltage SRAM Array Total Area. 2333-2337 - Joseph Reddington, Kubilay Atasu:
Complexity of Computing Convex Subgraphs in Custom Instruction Synthesis. 2337-2341 - Luca Gaetano Amarù, Maurizio Martina, Guido Masera:
High Speed Architectures for Finding the First two Maximum/Minimum Values. 2342-2346 - Wai-Kei Mak, Chris Chu:
Rethinking the Wirelength Benefit of 3-D Integration. 2346-2351 - Toru Tanzawa:
A Behavior Model of an On-Chip High Voltage Generator for Fast, System-Level Simulation. 2351-2355
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-27 20:18 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
