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ORCID25th PATMOS 2015: Salvador, Brazil
- 25th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2015, Salvador, Brazil, September 1-4, 2015. IEEE 2015, ISBN 978-1-4673-9419-2
Session 1: Circuit and system optimization
- Eduardo Valentin, Mario Salvatierra, Rosiane de Freitas, Raimundo S. Barreto
:
Response time schedulability analysis for hard real-time systems accounting DVFS latency on heterogeneous cluster-based platform. 1-8 - Krzysztof Kepa, Ritesh Soni, Peter M. Athanas:
Inferring custom architectures from OpenCL. 9-16 - Viviane Lucy Santos de Souza, Abel G. Silva-Filho, V. C. Wanderely:
ABeeMap: A mapping algorithm based on multi-objective Artificial Bee Colony. 17-24 - Anastasis Keliris, Vasilis Dimitsas, Olympia Kremmyda, Dimitris Gizopoulos, Michail Maniatakos:
Efficient parallelization of the Discrete Wavelet Transform algorithm using memory-oblivious optimizations. 25-32 - Hamid Mushtaq, Zaid Al-Ars, Koen Bertels:
Calculation of worst-case execution time for multicore processors using deterministic execution. 33-39 - Vincent Canals, Antoni Morro, Antoni Oliver, Miquel Lleo Alomar, Josep L. Rosselló:
An unconventional computing technique for ultra-fast and ultra-low power data mining. 40-46
Session 2: System-Level Design and Management
- Smruti R. Sarangi, Rajshekar Kalayappan, Prathmesh Kallurkar, Seep Goel, Eldhose Peter:
Tejas: A java based versatile micro-architectural simulator. 47-54 - Soundous Chairat, Edith Beigné, Marc Belleville:
Dedicated network for distributed configuration in a mixed-signal Wireless Sensor Node circuit. 55-62 - Anca Mariana Molnos, Warody Lombardi, Diego Puschini, Julien Mottin, Suzanne Lesecq, Arnaud Tonda:
Energy management via PI control for data parallel applications with throughput constraints. 63-70 - Nelson Alves Ferreira Neto, Joaquim Ranyere S. de Oliveira, Wagner Luiz Alves de Oliveira, João Carlos N. Bittencourt:
VLSI architecture design and implementation of a LDPC encoder for the IEEE 802.22 WRAN standard. 71-76
Session 3: Low Power Design Techniques
- Jordan Innocenti, Loïc Welter, Nicolas Borrel, Franck Julien, Jean-Michel Portal, Jacques Sonzogni, Laurent Lopez, Pascal Masson, Stephan Niel, Philippe Dreux, Julia Castellan:
Dynamic current reduction of CMOS digital circuits through design and process optimization. 77-81 - Emilie Garat, David Coriat, Edith Beigné, Leandro Stefanazzi:
Unified Power Format (UPF) methodology in a vendor independent flow. 82-88 - Ron Diamant, Ran Ginosar, Christos P. Sotiriou:
Asynchronous sub-threshold ultra-low power processor. 89-96 - Bao Le, Djordje Maksimovic, Dipanjan Sengupta, Erhan Ergin, Ryan Berryhill, Andreas G. Veneris:
Constructing stability-based clock gating with hierarchical clustering. 97-102 - Sheng Yang, Rishad A. Shafik, Geoff V. Merrett, Edward A. Stott, Joshua M. Levine, James J. Davis, Bashir M. Al-Hashimi:
Adaptive energy minimization of embedded heterogeneous systems using regression-based learning. 103-110 - Maurício Altieri, Suzanne Lesecq, Diego Puschini, Olivier Héron, Edith Beigné, Jorge Rodas:
Evaluation and mitigation of aging effects on a digital on-chip voltage and temperature sensor. 111-117
Session 4: Reliability, Noise Reduction And Robustness
- Rodrigo Fonseca Rocha Soares, Frank Sill Torres, Dirk Timmermann:
Exploration of technology parameter values of integrated circuit technologies. 118-125 - Milan Babic, Xin Fan, Milos Krstic:
Frequency-domain modeling of ground bounce and substrate noise for synchronous and GALS systems. 126-131 - Fabio Frustaci, David T. Blaauw, Dennis Sylvester, Massimo Alioto:
Better-than-voltage scaling energy reduction in approximate SRAMs via bit dropping and bit reuse. 132-139 - Robert Najvirt, Andreas Steininger:
A versatile and reliable glitch filter for clocks. 140-147
Session 5: Energy-Efficiency Systems
- Roger Caputo-Llanos, Diego Sousa, Marco Terres, Guilherme Bontorin, Ricardo Reis, Marcelo O. Johann:
Energy-efficient Level Shifter topology. 148-151 - Lisa J. K. Durbeck, Joseph G. Tront, Nicholas J. Macias:
Energy efficiency of Zipf traffic distributions within Facebook's data center fabric architecture. 152-160 - Victor Lira, Eduardo Tavares:
Energy-aware mapping for dependable virtual networks. 161-168 - Sidinei Ghissoni, Eduardo Costa, Ricardo Reis:
Reusing smaller optimized FFT blocks for the realization of larger power-efficient radix-2 FFTs. 169-176 - Ismael Seidel, André Beims Bräscher, José Luís Güntzel:
Combining Pel Decimation with Partial Distortion Elimination to increase SAD energy efficiency. 177-184 - K. Gao, Y. Xu, Delong Shang, Fei Xia, Alex Yakovlev:
Wideband dynamic voltage sensing mechanism for EH systems. 185-192
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