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ORCIDITC 2008: Santa Clara, California, USA
- Douglas Young, Nur A. Touba:
2008 IEEE International Test Conference, ITC 2008, Santa Clara, California, USA, October 26-31, 2008. IEEE Computer Society 2008, ISBN 978-1-4244-2403-0 - Mike Lydon:
Managing Test in the End-to-End, Mega Supply Chain. - Jan M. Rabaey:
Computing at the Crossroads (And What Does it Mean to Verification and Test?). - Robert A. Pease:
Having FUN with Analog Test. - Jeff Rearick:
This is a Test: How to Tell if DFT and Test Are Adding Value to Your Company. - Sean H. Wu, Dragoljub Gagi Drmanac, Li-C. Wang
:
A Study of Outlier Analysis Techniques for Delay Testing. 1-10 - Peter M. O'Neill:
Production Multivariate Outlier Detection Using Principal Components. 1-10 - Anne Gattiker:
Unraveling Variability for Process/Product Improvement. 1-9 - Tim Wood, Grady Giles, Chris Kiszely, Martin Schuessler, Daniela Toneva, Joel Irby, Michael Mateja:
The Test Features of the Quad-Core AMD Opteron- Microprocessor. 1-10 - Ishwar Parulkar, Sriram Anandakumar, Gaurav Agarwal, Gordon Liu, Krishna Rajan, Frank Chiu, Rajesh Pendurkar:
DFX of a 3rd Generation, 16-core/32-thread UltraSPARC- CMT Microprocessor. 1-10 - Grady Giles, Jing Wang, Anuja Sehgal, Kedarnath J. Balakrishnan, James Wingfield:
Test Access Mechanism for Multiple Identical Cores. 1-10 - Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
High Throughput Diagnosis via Compression of Failure Data in Embedded Memory BIST. 1-10 - Alexandre Ney, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs. 1-10 - Wei Kong, Paul C. Parries, G. Wang, Subramanian S. Iyer:
Analysis of Retention Time Distribution of Embedded DRAM - A New Method to Characterize Across-Chip Threshold Voltage Variation. 1-7 - Anne Meixner, Akira Kakizawa, Benoit Provost, Serge Bedwani:
External Loopback Testing Experiences with High Speed Serial Interfaces. 1-10 - William Fritzsche, Asim E. Haque:
Low cost testing of multi-GBit device pins with ATE assisted loopback instrument. 1-8 - Thomas Nirmaier, Jose Torres Zaguirre, Eric Liau, Wolfgang Spirkl, Armin Rettenberger, Doris Schmitt-Landsiedel:
Efficient High-Speed Interface Verification and Fault Analysis. 1-9 - Anjali Vij, Richard Ratliff:
Implementation Update: Logic Mapping On SPARC- Microprocessors. 1-10 - Jaekwang Lee, Edward J. McCluskey:
Failing Frequency Signature Analysis. 1-8 - Saeed Shamshiri, Peter Lisherness, Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng:
A Cost Analysis Framework for Multi-core Systems with Spares. 1-8 - Adit D. Singh:
Scan Based Testing of Dual/Multi Core Processors for Small Delay Defects. 1-8 - Rajeshwary Tayade, Jacob A. Abraham:
On-chip Programmable Capture for Accurate Path Delay Test and Characterization. 1-10 - Kelageri Nagaraj, Sandip Kundu:
An Automatic Post Silicon Clock Tuning System for Improving System Performance based on Tester Measurements. 1-8 - Surendra Bommu, Kameshwar Chandrasekar, Rahul Kundu, Sanjay Sengupta:
CONCAT: CONflict Driven Learning in ATPG for Industrial designs. 1-10 - Weixin Wu, Michael S. Hsiao:
SAT-based State Justification with Adaptive Mining of Invariants. 1-10 - Saeed Mirzaeian, Feijun (Frank) Zheng, Kwang-Ting (Tim) Cheng:
RTL Error Diagnosis Using a Word-Level SAT-Solver. 1-8 - Omer Vikinski, Shaul Lupo, Gregory Sizikov, Chee Yee Chung:
Embedded Power Delivery Decoupling in Small Form Factor Test Sockets. 1-8 - Thomas P. Warwick, Gustavo Rivera, David Waite, James Russell, Jeffrey Smith:
Measurement Repeatability for RF Test Within the Load-board Constraints of High Density and Fine Pitch SOC Applications. 1-10 - Gyu-Yeol Kim, Eon-Jo Byunb, Ki-Sang Kang, Young-Hyun Jun, Bai-Sun Kong:
Wafer-Level Characterization of Probecards using NAC Probing. 1-9 - Vivek Chickermane, Patrick R. Gallagher Jr., James Sage, Paul Yuan, Krishna Chakravadhanula:
A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs. 1-10 - Sobeeh Almukhaizim, Ozgur Sinanoglu:
Peak Power Reduction Through Dynamic Partitioning of Scan Chains. 1-10 - Benoit Nadeau-Dostie, Kiyoshi Takeshita, Jean-Francois Cote:
Power-Aware At-Speed Scan Test Methodology for Circuits with Synchronous Clocks. 1-10 - Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman:
Time-dependent Behaviour of Full Open Defects in Interconnect Lines. 1-10 - Aswin Sreedhar, Sandip Kundu:
Statistical Yield Modeling for Sub-wavelength Lithography. 1-8 - Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz:
Detection of Internal Stuck-open Faults in Scan Chains. 1-10 - Myron Schneider, Ayub Shafi:
Engineering Test Coverage on Complex Sockets. 1-9 - Dave F. Dubberke, James J. Grealish, Bill Van Dick:
Solving In-Circuit Defect Coverage Holes with a Novel Boundary Scan Application. 1-9 - Dayton Norrgard, Kenneth P. Parker:
Augmenting Boundary-Scan Tests for Enhanced Defect Coverage. 1-8 - Andreas Merentitis, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos:
Low Energy On-Line SBST of Embedded Processors. 1-10 - Javier Carretero, Xavier Vera, Pedro Chaparro, Jaume Abella:
On-line Failure Detection in Memory Order Buffers. 1-10 - Hiroaki Inoue, Yanjing Li, Subhasish Mitra:
VAST: Virtualization-Assisted Concurrent Autonomous Self-Test. 1-10 - Meng-Fan Wu, Jiun-Lang Huang, Xiaoqing Wen, Kohei Miyase:
Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing. 1-10 - Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Low Power Scan Shift and Capture in the EDT Environment. 1-10 - Shlomi Sde-Paz, Eyal Salomon:
Frequency and Power Correlation between At-Speed Scan and Functional Tests. 1-9 - Fei Wang, Yu Hu, Huawei Li, Xiaowei Li, Jing Ye, Yu Huang:
Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects. 1-10 - Pouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir:
Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - the methodology explained. 1-10 - Manish Sharma, Brady Benware, Lei Ling, David Abercrombie, Lincoln Lee, Martin Keim, Huaxing Tang, Wu-Tung Cheng, Ting-Pu Tai, Yi-Jung Chang, Reinhart Lin, Albert Mann:
Efficiently Performing Yield Enhancements by Identifying Dominant Physical Root Cause from Test Fail Data. 1-9 - Brandon Chu:
Solder Bead on High Density Interconnect Printed Circuit Board. 1-5 - Steve Hird, Reggie Weng:
Finding Power/Ground Defects on Connectors - Case Study. 1-4 - Laurent Souef, Christophe Eychenne, Emmanuel Alie:
Architecture for Testing Multi-Voltage Domain SOC. 1-10 - Jeroen Geuzebroek, Bart Vermeulen:
Integration of Hardware Assertions in Systems-on-Chip. 1-10 - Ho Fai Ko, Adam B. Kinsman, Nicola Nicolici:
Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs. 1-10 - Xiaochun Yu, Ronald D. Blanton:
An Effective and Flexible Multiple Defect Diagnosis Methodology Using Error Propagation Analysis. 1-9 - Ruifeng Guo, Liyang Lai, Yu Huang, Wu-Tung Cheng:
Detection and Diagnosis of Static Scan Cell Internal Defect. 1-10 - Peilin Song, Stephen Ippolito, Franco Stellari, John Sylvestri, Tim Diemoz, George Smith, Paul Muench, Norm James, Seongwon Kim, Hector Saenz:
Optical Diagnostics for IBM POWER6- Microprocessor. 1-9 - Tung N. Pham, Frances Clougherty, Gerard Salem, James M. Crafts, Jon Tetzloff, Pamela Moczygemba, Timothy M. Skergan:
Functional Test and Speed/Power Sorting of the IBM POWER6 and Z10 Processors. 1-7 - Liang-Chi Chen, Paul Dickinson, Prasad Mantri, Murali M. R. Gala, Peter Dahlgren, Subhra Bhattacharya, Olivier Caty, Kevin Woodling, Thomas A. Ziaja, David Curwen, Wendy Yee, Ellen Su, Guixiang Gu, Tim Nguyen:
Transition Test on UltraSPARC- T2 Microprocessor. 1-10 - Heiko Ahrens, Rolf Schlagenhaft, Helmut Lang, V. Srinivasan, Enrico Bruzzano:
DFT Architecture for Automotive Microprocessors using On-Chip Scan Compression supporting Dual Vendor ATPG. 1-10 - Ganesh Srinivasan, Hui-Chuan Chao, Friedrich Taenzler:
Octal-Site EVM Tests for WLAN Transceivers on "Very" Low-Cost ATE Platforms. 1-9 - Erkan Acar, Sule Ozev, Ganesh Srinivasan, Friedrich Taenzler:
Optimized EVM Testing for IEEE 802.11a/n RF ICs. 1-10 - Vishwanath Natarajan, Hyun Woo Choi, Deuk Lee, Rajarajan Senguttuvan, Abhijit Chatterjee:
EVM Testing of Wireless OFDM Transceivers Using Intelligent Back-End Digital Signal Processing Algorithms. 1-10 - Stefan Eichenberger, Jeroen Geuzebroek, Camelia Hora, Bram Kruseman, Ananta K. Majhi:
Towards a World Without Test Escapes: The Use of Volume Diagnosis to Improve Test Quality. 1-10 - Kenneth M. Butler, John M. Carulli Jr., Jayashree Saxena:
Modeling Test Escape Rate as a Function of Multiple Coverages. 1-9 - Yen-Tzu Lin, Osei Poku, Ronald D. Blanton, Phil Nigh, Peter Lloyd, Vikram Iyengar:
Evaluating the Effectiveness of Physically-Aware N-Detect Test using Real Silicon. 1-9 - Akinori Maeda:
A Method to Generate a Very Low Distortion, High Frequency Sine Waveform Using an AWG. 1-8 - Bethany Van Wagenen, Jon Vollmar, Dan Thornton:
Leveraging IEEE 1641 for Tester-Independent ATE Software. 1-10 - Ernst Aderholz, Heiko Ahrens, Michael Rohleder:
Bridging the gap between Design and Test Engineering for Functional Pattern Development. 1-10 - Homa Alemzadeh, Stefano Di Carlo, Fatemeh Refan, Paolo Prinetto, Zainalabedin Navabi:
"Plug & Test" at System Level via Testable TLM Primitives. 1-10 - Waleed K. Al-Assadi, Sindhu Kakarla:
Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits. 1-9 - Brian Moore, Marc Mangrum, Chris Sellathamby, Md. Mahbub Reja, T. Weng, Brenda Bai, Edwin Walter Reid, Igor M. Filanovsky, Steven Slupsky:
Non-contact Testing for SoC and RCP (SIPs) at Advanced Nodes. 1-10 - Naghmeh Karimi, Michail Maniatakos, Abhijit Jas, Yiorgos Makris:
On the Correlation between Controller Faults and Instruction-Level Errors in Modern Microprocessors. 1-10 - Kundan Nepal, Nuno Alves, Jennifer Dworak, R. Iris Bahar:
Using Implications for Online Error Detection. 1-10 - Syed Zafar Shazli, Mohammed A. Abdul-Aziz, Mehdi Baradaran Tahoori, David R. Kaeli:
A Field Analysis of System-level Effects of Soft Errors Occurring in Microprocessors used in Information Systems. 1-10 - Akira Katayama, Tomoaki Yabe, Osamu Hirabayashi, Yasuhisa Takeyama, Keiichi Kushida, Takahiko Sasaki, Nobuaki Otsuka:
Direct Cell-Stability Test Techniques for an SRAM Macro with Asymmetric Cell-Bias-Voltage Modulation. 1-7 - Tsu-Wei Tseng, Jin-Fu Li:
A Shared Parallel Built-In Self-Repair Scheme for Random Access Memories in SOCs. 1-9 - Chi-Min Chang, Mango Chia-Tso Chao, Rei-Fu Huang, Ding-Yuan Chen:
Testing Methodology of Embedded DRAMs. 1-9 - Mridul Agarwal, Varsha Balakrishnan, Anshuman Bhuyan, Kyunglok Kim, Bipul C. Paul, Wenping Wang, Bo Yang, Yu Cao, Subhasish Mitra:
Optimized Circuit Failure Prediction for Aging: Practicality and Promise. 1-10 - Feng Yuan, Qiang Xu:
SoC Test Architecture Design and Optimization Considering Power Supply Noise Effects. 1-9 - Kan Takeuchi, Genichi Tanaka, Hiroaki Matsushita, Kenichi Yoshizumi, Yusaku Katsuki, Takao Sato:
Observations of Supply-Voltage-Noise Dispersion in Sub-nsec. 1-8 - Mamoru Tamba:
A Hybrid A/D Converter with 120dB SNR and -125dB THD. 1-9 - Sadok Aouini, Gordon W. Roberts:
Generating Test Signals for Noise-Based NPR/ACPR Type Tests in Production. 1-9 - David C. Keezer, Dany Minier, Patrice Ducharme, A. M. Majid:
An Electronic Module for 12.8 Gbps Multiplexing and Loopback Test. 1-9 - I-De Huang, Yi-Shing Chang, Suriyaprakash Natarajan, Ramesh Sharma, Sandeep K. Gupta:
On Accelerating Path Delay Fault Simulation of Long Test Sequences. 1-9 - Dheepakkumaran Jayaraman, Edward Flanigan, Spyros Tragoudas:
Implicit Identification of Non-Robustly Unsensitizable Paths using Bounded Delay Model. 1-10 - Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor:
Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay Defects. 1-10 - Kenneth P. Parker, Neil G. Jacobson:
Boundary-Scan Testing of Power/Ground Pins. 1-8 - Brendan Mullane, Michael Higgins, Ciaran MacNamee:
IEEE 1500 Core Wrapper Optimization Techniques and Implementation. 1-10 - Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, Chia-Hsien Yeh, Wei-Shin Wang, Hao-Jan Chao, Jianghao Guo, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li:
Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard. 1-9 - Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor, Georg Mueller:
Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs. 1-10 - Junghyun Nam, Sunghoon Chun, Gibum Koo, Yanggi Kim, Byungsoo Moon, Jonghyoung Lim, Jaehoon Joo, Sangseok Kang, Hoonjung Kim, Kyeongseon Shin, Kisang Kang, Sungho Kang:
A New Wafer Level Latent Defect Screening Methodology for Highly Reliable DRAM Using a Response Surface Method. 1-10 - Olivier Ginez, Jean-Michel Portal, Hassen Aziza:
A High-Speed Structural Method for Testing Address Decoder Faults in Flash Memories. 1-10 - Vincent Mao, Chris Dwyer, Krishnendu Chakrabarty:
Fabrication Defects and Fault Models for DNA Self-Assembled Nanoelectronics. 1-10 - Yang Zhao, Tao Xu, Krishnendu Chakrabarty:
Built-in Self-Test and Fault Diagnosis for Lab-on-Chip Using Digital Microfluidic Logic Gates. 1-10 - Mehrdad Majzoobi, Farinaz Koushanfar, Miodrag Potkonjak:
Testing Techniques for Hardware Security. 1-10 - Le Jin:
Linearity Test Time Reduction for Analog-to-Digital Converters Using the Kalman Filter with Experimental Parameter Estimation. 1-8 - Wei Jiang, Vishwani D. Agrawal:
Built-in Self-Calibration of On-chip DAC and ADC. 1-10 - Takahiro J. Yamaguchi, Masayuki Kawabata, Mani Soma, Masahiro Ishida, K. Sawami, Koichiro Uekusa:
A New Method for Measuring Aperture Jitter in ADC Output and Its Application to ENOB Testing. 1-9 - Xijiang Lin, Janusz Rajski:
Test Generation for Interconnect Opens. 1-7 - Jeremy Lee, Mohammad Tehranipoor:
A Novel Pattern Generation Framework for Inducing Maximum Crosstalk Effects on Delay-Sensitive Paths. 1-10 - Stefan Hillebrecht, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng:
Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model. 1-10 - Jason Doege, Alfred L. Crouch:
The Advantages of Limiting P1687 to a Restricted Subset. 1-8 - Michele Portolan, Suresh Goyal, Bradford G. Van Treuren, Chen-Huan Chiang, Tapan J. Chakraborty, Thomas B. Cook:
A New Language Approach for IJTAG. 1-10 - Bradford G. Van Treuren, Chen-Huan Chiang, Kenneth Honaker:
Problems Using Boundary-Scan for Memory Cluster Tests. 1-10 - Peter Wohl, John A. Waicukauski, Frederic Neuveux:
Increasing Scan Compression by Using X-chains. 1-10 - Ozgur Sinanoglu:
Align-Encode: Improving the Encoding Capability of Test Stimulus Decompressors. 1-10 - Intaik Park, Edward J. McCluskey:
Launch-on-Shift-Capture Transition Tests. 1-9 - Mike P. Li:
Jitter and Signal Integrity Verification for Synchronous and Asynchronous I/Os at Multiple to 10 GHz/Gbps. 1-6 - T. M. Mak:
Jitters in high performance microprocessors. 1-6 - Jose Moreira, Heidi Barnes, Hiroshi Kaga, Michael Comai, Bernhard Roth, Morgan Culver:
Beyond 10 Gbps? Challenges of Characterizing Future I/O Interfaces with Automated Test Equipment. 1-10 - John Malian, Bill Eklow:
Embedded Testing in an In-Circuit Test Environment. 1-6 - Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn:
Hardware-based Error Rate Testing of Digital Baseband Communication Systems. 1-10 - Ajay Khoche, Phil Burlison, John Rowe, Glenn Plowman:
A Tutorial on STDF Fail Datalog Standard. 1-10 - Brice Achkir, Pavel Zivny, Bill Eklow:
Parametric Testing of Optical Interfaces. 1 - Scott Davidson:
Justifying DFT with a Hierarchical Top-Down Cost-Benefit Model. 1-10 - Louis Y. Ungar:
The Economics of Harm Prevention through Design for Testability. 1-8 - Overview of IEEE P1450.6.2 Standard; Creating CTL Model For Memory Test and Repair. 1
- Heiko Ehrenberg:
IEEE P1581 drastically simplifies connectivity test for memory devices. 1 - Swapnil Bahl, Rajiv Sarkar, Akhil Garg:
Low Power Test. 1 - Geng-Ming Chiu, James Chien-Mo Li:
IEEE 1500 Compatible Secure Test Wrapper For Embedded IP Cores. 1 - Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie:
Test-Access Solutions for Three-Dimensional SOCs. 1 - Anders Larsson, Xin Zhang, Erik Larsson, Krishnendu Chakrabarty:
SOC Test Optimization with Compression-Technique Selection. 1 - Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
SoC Yield Improvement: Redundant Architectures to the Rescue? 1 - Arie Margulis, David Akselrod, Tim Wood, Sopho Metsis:
Platform Independent Test Access Port Architecture. 1 - Armin Alaghi, Mahshid Sedghi, Naghmeh Karimi, Zainalabedin Navabi:
NoC Reconfiguration for Utilizing the Largest Fault-free Connected Sub-structure. 1 - Satoshi Komatsu:
VLSI Test Exercise Courses for Students in EE Department. 1 - Masayuki Arai, Kazuhiko Iwasaki, Michinobu Nakao, Iwao Suzuki:
Hardware Overhead Reduction for Memory BIST. 1 - Chung-Fu Lin, Chia-Fu Huang, De-Chung Lu, Chih-Chiang Hsu, Wen-Tsung Chiu, Yu-Wei Chen, Yeong-Jar Chang:
A Low-Cost Programmable Memory BIST Design for Multiple Memory Instances. 1 - Jonathan Phelps, Chuck Johnson, Corey Goodrich, Aman Kokrady:
The Importance of Functional-Like Access for Memory Test. 1 - Jaehoon Song, Taejin Jung, Junseop Lee, Hyeran Jeong, Byeongjin Kim, Sungju Park:
An Efficient Secure Scan Design for an SoC Embedding AES Core. 1 - Jing Ye, Fei Wang, Yu Hu, Xiaowei Li:
Diagnosis of Mask-Effect Multiple Timing Faults in Scan Chains. 1 - Wei-Chih Liu, Wei-Lin Tsai, Hsiu-Ting Lin, James Chien-Mo Li:
Diagnosis of Logic-to-chain Bridging Faults. 1 - Junxia Ma, Jeremy Lee, Mohammad Tehranipoor:
Power Distribution Failure Analysis Using Transition-Delay Fault Patterns. 1 - Lin Huang, Qiang Xu:
Is It Cost-Effective to Achieve Very High Fault Coverage for Testing Homogeneous SoCs with Core-Level Redundancy? 1 - Bradford G. Van Treuren:
System JTAG Initiative Group Advancements. 1 - Xiao Liu, Feng Yuan, Qiang Xu:
A Generic Framework for Scan Capture Power Reduction in Test Compression Environment. 1 - Jayant D'Souza, Subramanian Mahadevan, Nilanjan Mukherjee, Graham Rhodes, Jocelyn Moreau, Thomas Droniou, Paul Armagnat, Damien Sartoretti:
High Test Quality in Low Pin Count Applications. 1 - Hsiu-Ting Lin, Jen-Yang Wen, James Li, Ming-Tung Chang, Min-Hsiu Tsai, Sheng-Chih Huang, Chili-Mou Tseng:
Capture and Shift Toggle Reduction (CASTR) ATPG to Minimize Peak Power Supply Noise. 1 - Che-Jen Jerry Chang, Takeo Kobayashi:
Test Quality Improvement with Timing-aware ATPG: Screening small delay defect case study. 1 - William J. Bowhers:
FPGA Time Measurement Module: Preliminary Results. 1 - Ziad Noun, Philippe Cauvet, Marie-Lise Flottes, David Andreu, Serge Bernard:
Wireless Test Structure for Integrated Systems. 1 - John Stewart, Temitope Animashaun:
Overview of a High Speed Top Side Socket Solution. 1 - Sounil Biswas, Ronald D. Blanton:
Improving the Accuracy of Test Compaction through Adaptive Test Update. 1 - Robert L. Franch, Phillip J. Restle, James K. Norman, William V. Huott, Joshua Friedrich, R. Dixon, Steve Weitzel, K. van Goor, Gerard Salem:
On-chip Timing Uncertainty Measurements on IBM Microprocessors. 1-7 - Amit Dutta, Srinivasulu Alampally, V. Prasanth, Rubin A. Parekhji:
DFT Implementationis for Striking the Right Balance between Test Cost and Test Quality for Automotive SOCs. 1-10 - Rajesh Raina:
Achieving Zero-Defects for Automotive Applications. 1-10 - Paolo Bernardi, Fabio Melchiori, Davide Pandini, Santo Pugliese, Davide Appello:
Robust Design-for-Productization Practices for High Quality Automotive Products. 1-9
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last updated on 2024-11-06 20:18 CET by the dblp team
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