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ORCIDHideo Nakamura
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2020 – today
- 2022
[c13]Jumpei Matsuura, Takahiro Kunii, Hiroshi Noborio, Katsuhiko Onishi, Hideo Nakamura:
Analysis of Changes Before, During, and After Simulated Postoperative Delirium Experience Using VR for Clinical Nurses. HCI (3) 2022: 194-204- 2021
- [c12]Jumpei Matsuura, Takahiro Kunii, Hiroshi Noborio, Kaoru Watanabe, Katsuhiko Onishi, Hideo Nakamura:
Development of a VR/HMD System for Simulating Several Scenarios of Post-Operative Delirium. HCI (2) 2021: 582-600
2010 – 2019
- 2019
- [c11]Hideo Nakamura, Munenori Tagawa:
Pitfall of heart rate variability analyses for autonomic nervous system activity with photoplethysmography. EMBC 2019: 1197-1200 - 2016
- [c10]Guo Xie, Zhuxin Wang, Xinhong Hei, Sei Takahashi, Hideo Nakamura:
Data-Based Axle Temperature Prediction of High Speed Train by Multiple Regression Analysis. CIS 2016: 349-353 - 2015
- [j9]Yinghong Wen, Yuan Cao, Wei Xu, Hideo Nakamura:
Cell-Specific Association for Heterogeneous Networks with Interference Control. IEICE Trans. Commun. 98-B(4): 653-660 (2015) - [c9]Hideo Nakamura:
Dynamic response of cardiac autonomic nervous system activity to habitual exercise during gradual variation of breathing frequency. EMBC 2015: 7712-7715 - 2014
- [j8]Baigen Cai
, Chengming Jin, Lian-chuan Ma, Yuan Cao, Hideo Nakamura:
Analysis on the application of on-chip redundancy in the safety-critical system. IEICE Electron. Express 11(9): 20140153 (2014) - [j7]Guo Xie, Xinhong Hei, Sei Takahashi, Hideo Nakamura:
A Strategy to Formalize Specification and Its Application to an Advanced Railway System. Int. J. Softw. Eng. Knowl. Eng. 24(3): 465-492 (2014) - [j6]Guo Xie, Xinhong Hei, Hiroshi Mochizuki, Sei Takahashi, Hideo Nakamura:
Safety and Reliability Estimation of Automatic Train Protection and Block System. Qual. Reliab. Eng. Int. 30(4): 463-472 (2014) - 2013
- [j5]Yuan Cao, Wei Xu, Hideo Nakamura:
Performance Enhanced Efficient Precoder Design with Power Allocation for Multiuser MIMO Downlinks. IEICE Trans. Commun. 96-B(7): 1962-1967 (2013) - [c8]Tomohiro Kuroda, Kikuo Hirano, Kazushige Sugimura, Satoshi Adachi, Hidetsugu Igarashi, Kazuo Ueshima, Hideo Nakamura, Masayuki Nambu, Takahiro Doi:
Applying NISHIJIN historical textile technique for e-Textile. EMBC 2013: 1226-1229 - 2011
- [c7]Guo Xie, Akira Asano, Sei Takahashi, Hideo Nakamura:
Study on Formal Specification of Automatic Train Protection and Block System for Local Line. SSIRI (Companion) 2011: 35-40
2000 – 2009
- 2008
- [c6]Xinhong Hei, Sei Takahashi, Hideo Nakamura:
Toward developing a Decentralized Railway Signalling System Using Petri Nets. RAM 2008: 851-855 - 2001
- [c5]Sei Takahashi, Munehisa Taira, Hidetaka Saegusa, Takehiko Hoshino, Hideo Nakamura:
Development of a Fail-Safe Microprocessor LSI with Self-Diagnosis Mechanism Depending on an M-Sequence Code Signature. PRDC 2001: 191-198 - [c4]Shigeto Hiraguri, Noriyuki Nishibori, Yasuko Hidaka, Takayuki Kasai, Hideo Nakamura:
Safety Analysis by Box Modeling Method of System Behavior -- Application to Train Control System. PRDC 2001: 375-378
1990 – 1999
- 1994
- [j4]Hideo Nakamura, Hisato Kobayashi, Takefumi Shimada:
Mobile robots on cylindrical surfaces. Adv. Robotics 9(2): 149-164 (1994) - [c3]Yutaka Hasegawa, Hideo Nakamura:
Experimental system of CARAT on the Joetsu Shinkansen line. VTC 1994: 1122-1125 - 1992
- [c2]Hideo Nakamura, Kiyoshi Takeshi:
Fault-Tolerant Microcomputer Design and Application for Railway Train Control. IFIP Congress (1) 1992: 652-658
1980 – 1989
- 1987
- [c1]Naoshi Uchihira, Kazunori Matsumoto, Shinichi Honiden, Hideo Nakamura:
MENDELS: Concurrent Program Synthesis System Using Temporal Logic. LP 1987: 50-68 - 1983
- [j3]Hideo Maejima, Koyo Katsura, Hideo Nakamura, Toshimasa Kihara:
The VLSI Control Structure of a CMOS Microcomputer. IEEE Micro 3(6): 9-16 (1983) - 1981
- [j2]Hideo Nakamura, Hirotugu Akaike:
Statistical identification for optimal control of supercritical thermal power plants. Autom. 17(1): 143-155 (1981) - 1980
- [j1]Tsuneo Funabashi, Katsuaki Takagi, Toshiro Tsukada, Hideo Nakamura, Michio Hara:
An NMOS Microcomputer Peripheral Interface Unit Incorporating an Analog-to-Digital Converter. IEEE Trans. Computers 29(2): 102-107 (1980)
Coauthor Index
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