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ORCIDChristoph Heer
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2010 – 2019
- 2019
[c16]Friedhelm Rostan, Dieter Ulrich, Christoph Heer, Allan Østergaard:
The Metop-Sg Sca wind Scatterometer: Cdr Development Status and Performance Overview. IGARSS 2019: 8332-8335- 2018
- [c15]Friedhelm Rostan, Dieter Ulrich, Eberhard Schied, Christoph Heer, Allan Østergaard:
In-Flight Calibration of the Metop-Sg Sca Wind Scatterometer. IGARSS 2018: 2019-2022 - [c14]Thomas Fügen, Eckhardt Sperlich, Christoph Heer, Sebastian Riegger, Carl Warren, Adriano Carbone, Florence Hélière:
The Biomass SAR Instrument: Development Status and Performance Overview. IGARSS 2018: 8571-8574 - 2016
- [c13]Grzegorz Adamiuk, Thomas Fügen, Christian Fischer, Bernhard Grafmueller, Friedhelm Rostan, Christoph Heer:
Verification of scan-on-receive beamforming for X-Band HRWS applications. IGARSS 2016: 2120-2122 - 2012
- [j2]Milos Krstic
, Xin Fan, Eckhard Grass, Luca Benini, Mohammad Reza Kakoee, Christoph Heer, Birgit Sanders, Alessandro Strano, Davide Bertozzi:
Evaluation of GALS Methods in Scaled CMOS Technology: Moonrake Chip Experience. Int. J. Embed. Real Time Commun. Syst. 3(4): 1-18 (2012) - [c12]Xin Fan, Milos Krstic, Eckhard Grass, Birgit Sanders, Christoph Heer:
Exploring pausible clocking based GALS design for 40-nm system integration. DATE 2012: 1118-1121 - 2011
- [c11]Milos Krstic, Xin Fan, Eckhard Grass, Christoph Heer, Birgit Sanders, Luca Benini, Mohammad Reza Kakoee, Alessandro Strano, Davide Bertozzi:
Moonrake chip - GALS demonstrator in 40 nm CMOS technology. SoC 2011: 9-13
2000 – 2009
- 2004
- [c10]Christian Piguet, Jacques Gautier, Christoph Heer, Ian O'Connor, Ulf Schlichtmann:
Extremely Low-Power Logic. DATE 2004: 656-663 - [c9]Christophe Layer, Hans-Jörg Pfleiderer, Christoph Heer:
A scalable compact architecture for the computation of integer binary logarithms through linear approximation. ISCAS (2) 2004: 421-424 - [p1]Christoph Heer, Ulf Schlichtmann:
Ultra-Low-Power Design: Device and Logic Design Approaches. Ultra Low-Power Electronics and Design 2004: 1-20 - 2003
- [c8]Ettore Amirante, Jürgen Fischer, Markus Lang, Agnese Bargagli-Stoffi, Jörg Berthold, Christoph Heer, Doris Schmitt-Landsiedel:
An ultra low-power adiabatic adder embedded in a standard 0.13μm CMOS environment. ESSCIRC 2003: 599-602 - [c7]Christoph Heer, Francis Soualle, Rolf Zahn, Rolf Reber:
Investigations on a new high resolution wide swath SAR concept. IGARSS 2003: 521-523 - [c6]Tim Schoenauer, Jörg Berthold, Christoph Heer:
Reduced Leverage of Dual Supply voltages in Ultra Deep Submicron Technologies. PATMOS 2003: 41-50 - 2002
- [j1]Mladen Berekovic, Peter Pirsch, Thorsten Selinger, Kai-Immo Wels, Carolina Miro, Anne Lafage, Christoph Heer, Giovanni Ghigo:
Architecture of an Image Rendering Co-Processor for MPEG-4 Visual Compositing. J. VLSI Signal Process. 31(2): 157-171 (2002) - 2001
- [c5]Christoph Heer, Andreas Kirstädter, Christian Sauer:
Self-routing crossbar switch with internal contention resolution. ICECS 2001: 693-696 - 2000
- [c4]Mladen Berekovic, Peter Pirsch, Thorsten Selinger, Kai-Immo Wels, Carolina Miro, Anne Lafage, Christoph Heer, Giovanni Ghigo:
Architecture of an Image Rendering Co-Processor for MPEG-4 Systems. ASAP 2000: 15-24 - [c3]Mladen Berekovic, Peter Pirsch, Thorsten Selinger, Kai-Immo Wels, Carolina Miro, Anne Lafage, Christoph Heer, Giovanni Ghigo:
Co-processor architecture for MPEG-4 main profile visual compositing. ISCAS 2000: 180-183 - [c2]Christoph Heer, Carolina Miro, Anne Lafage, Mladen Berekovic, Giovanni Ghigo, Thorsten Selinger, Kai-Immo Wels:
Coprocessor architecture for MPEG-4 video object rendering. VCIP 2000: 1451-1458
1990 – 1999
- 1999
- [c1]Christoph Heer, Carolina Miro, Anne Lafage, Mladen Berekovic, Giovanni Ghigo, Thorsten Selinger, Kai-Immo Wels:
Design and architecture of the MPEG-4 video rendering co-processor 'TANGRAM'. ICECS 1999: 1205-1210 - 1995
- [b1]Christoph Heer:
Entwurfsmethode für selbstgetaktete VLSI-Datenpfadarchitekturen. University of Ulm, Germany, Shaker 1995, ISBN 978-3-8265-0708-3, pp. 1-128
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