default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDChung-Ho Chen
Person information
Other persons with a similar name
SPARQL queries 
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2020 – today
- 2024
[c44]Ta-Chun Lo, Shan-Hong Yang, Jyh-Biau Chang, Chung-Ho Chen, Ce-Kuen Shieh:
A Two-Phase Multi-Class Botnet Labeling Approach for Real-World Traffic. ICAIIC 2024: 1-6- 2020
- [c43]Tsung-Han Tsou, Dun-Jie Chen, Sheng-Yang Hung, Yu-Hsiang Wang, Chung-Ho Chen:
Optimization of Stride Prefetching Mechanism and Dependent Warp Scheduling on GPGPU. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [c42]Yu-Xiang Su, Jhi-Han Jheng, Dun-Jie Chen, Chung-Ho Chen:
Development of an Open ISA GPGPU for Edge Device Machine Learning Applications. ICUFN 2019: 214-217 - [c41]Min-Zhi Ji, Wei-Chung Tseng, Ting-Jia Wu, Bo-Rong Lin, Chung-Ho Chen:
Micro Darknet For Inference: ESL reference for inference accelerator design. ISOCC 2019: 69-70 - 2018
- [j30]Kuan-Chung Chen
, Chung-Ho Chen:
Enabling SIMT Execution Model on Homogeneous Multi-Core System. ACM Trans. Archit. Code Optim. 15(1): 6:1-6:26 (2018) - [c40]Sen-Chih Tsai, Yu-Xiang Su, Yu-Han Chin, Wei-Zhong Ceng, Chung-Ho Chen:
Kernel Aware Warp Scheduler. ISCAS 2018: 1-5 - [c39]Chung-Ho Chen:
A glance of the CASLab HSAIL SIMT GPU for OpenCL and TensorFlow applications. VLSI-DAT 2018: 1 - 2017
- [j29]Ching-Wen Lin, Chung-Ho Chen:
A Processor and Cache Online Self-Testing Methodology for OS-Managed Platform. IEEE Trans. Very Large Scale Integr. Syst. 25(8): 2346-2359 (2017) - [c38]Ching-Wen Lin, Chung-Ho Chen:
Processor shield for L1 data cache software-based on-line self-testing. ASP-DAC 2017: 420-425 - 2016
- [c37]Ching-Wen Lin, Chung-Ho Chen:
A processor shield for software-based on-line self-test. APCCAS 2016: 149-152 - [c36]Liang-Ying Lu, Ching-Yao Chang, Zhao-Hong Chen, Bo-Ting Yeh, Tai-Hua Lu, Peng-Yu Chen, Pin-Hao Tang, Kuen-Jong Lee, Lih-Yih Chiou, Soon-Jyh Chang, Chien-Hung Tsai, Chung-Ho Chen, Jai-Ming Lin:
A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. ASP-DAC 2016: 17-18 - [c35]Yun-Chi Huang, Kuan-Chieh Hsu, Wan-shan Hsieh, Chen-Chieh Wang, Chia-Han Lu, Chung-Ho Chen:
Dynamic SIMD re-convergence with paired-path comparison. ISCAS 2016: 233-236 - 2015
- [c34]Chien-Hsuan Yen, Chung-Ho Chen, Kuan-Chung Chen:
A memory-efficient NoC system for OpenCL many-core platform. ISCAS 2015: 1386-1389 - 2014
- [j28]En-Hao Chang, Chen-Chieh Wang, Chien-Te Liu, Kuan-Chung Chen, Chung-Ho Chen:
Virtualization Technology for TCP/IP Offload Engine. IEEE Trans. Cloud Comput. 2(2): 117-129 (2014) - [c33]Ching-Wen Lin, Chung-Ho Chen:
Unambiguous I-cache testing using software-based self-testing methodology. ISCAS 2014: 1756-1759 - [c32]Kuan-Chung Chen, Chung-Ho Chen:
An OpenCL runtime system for a heterogeneous many-core virtual platform. ISCAS 2014: 2197-2200 - 2013
- [j27]Chen-Chieh Wang, Chung-Ho Chen:
A System-Level Network Virtual Platform for IPsec Processor Development. IEICE Trans. Inf. Syst. 96-D(5): 1095-1104 (2013) - [c31]Chien-Te Liu, Kuan-Chung Chen, Chung-Ho Chen:
CASL hypervisor and its virtualization platform. ISCAS 2013: 1224-1227 - [c30]Tzu-Hsuan Hsu, Ching-Wen Lin, Chung-Ho Chen:
Using condition flag prediction to improve the performance of out-of-order processors. ISCAS 2013: 1240-1243 - 2012
- [c29]Eric Shianda Yu, Chung-Ho Chen:
A SIMD-accelerated software rendering pipeline for 3D graphics processing. APCCAS 2012: 440-443 - [c28]Chen-Chieh Wang, Sheng-Hsin Lo, Yao-Ning Liu, Chung-Ho Chen:
NetVP: A system-level NETwork Virtual Platform for network accelerator development. ISCAS 2012: 249-252 - [c27]Hsu-Yao Huang, Chi-Yuan Huang, Chung-Ho Chen:
Tile-based GPU optimizations through ESL full system simulation. ISCAS 2012: 1327-1330 - 2011
- [j26]Chung-Ho Chen, Chih-Lun Lu:
Optimum profit model based on order quantity, product price, and process quality level. Expert Syst. Appl. 38(6): 7886-7893 (2011) - [j25]Chung-Ho Chen, Chih-Lun Lu:
Optimum profit model considering production, quality and sale problem. Int. J. Syst. Sci. 42(12): 1917-1933 (2011) - [j24]Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee:
Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores. IEEE Trans. Very Large Scale Integr. Syst. 19(3): 516-520 (2011) - [j23]Yi-Ying Tsai, Chung-Ho Chen:
Energy-Efficient Trace Reuse Cache for Embedded Processors. IEEE Trans. Very Large Scale Integr. Syst. 19(9): 1681-1694 (2011) - [c26]Yi-Li Lin, Wei-Tso Chen, Alvin W. Y. Su, Da-Wei Chang, Chung-Ho Chen:
A low cost, low power, high scalability and dependability processor-cluster platform. SIES 2011: 95-98 - 2010
- [j22]Michael Boon Chong Khoo, Zhang Wu, Chung-Ho Chen, Kah Wai Yeong:
Using one EWMA chart to jointly monitor the process mean and variance. Comput. Stat. 25(2): 299-316 (2010) - [j21]Chung-Ho Chen, Wan-Lin Chang:
Optimal design of expected lifetime and warranty period for product with quality loss and inspection error. Expert Syst. Appl. 37(4): 3521-3526 (2010) - [c25]Shye-Tzeng Shen, Shin-Ying Lee, Chung-Ho Chen:
Full system simulation with QEMU: An approach to multi-view 3D GPU design. ISCAS 2010: 3877-3880
2000 – 2009
- 2009
- [j20]Chung-Ho Chen, Michael B. C. Khoo:
Optimum process mean and manufacturing quantity settings for serial production system under the quality loss and rectifying inspection plan. Comput. Ind. Eng. 57(3): 1080-1088 (2009) - [j19]Chung-Ho Chen, Hui-Sung Kao:
The determination of optimum process mean and screening limits based on quality loss function. Expert Syst. Appl. 36(3): 7332-7335 (2009) - [c24]Jing-Wun Lin, Chen-Chieh Wang, Chin-Yao Chang, Chung-Ho Chen, Kuen-Jong Lee, Yuan-Hua Chu, Jen-Chieh Yeh, Ying-Chuan Hsiao:
Full System Simulation and Verification Framework. IAS 2009: 165-168 - 2008
- [j18]Chung-Ho Chen:
Economic Production Run Length and warranty Period for Product with Weibull Lifetime. Asia Pac. J. Oper. Res. 25(6): 753-764 (2008) - [j17]Wei-Cheng Lin, Chung-Ho Chen:
Frame Buffer Access Reduction for MPEG Video Decoder. IEEE Trans. Circuits Syst. Video Technol. 18(10): 1452-1456 (2008) - [j16]Chung-Ming Chen, Chung-Ho Chen:
Configurable VLSI Architecture for Deblocking Filter in H.264/AVC. IEEE Trans. Very Large Scale Integr. Syst. 16(8): 1072-1082 (2008) - [c23]Yi-Cheng Lin, Yi-Ying Tsai, Kuen-Jong Lee, Cheng-Wei Yen, Chung-Ho Chen:
A Software-Based Test Methodology for Direct-Mapped Data Cache. ATS 2008: 363-368 - [c22]Wei-Cheng Lin, Chung-Ho Chen:
Avoiding unnecessary frame memory access and multi-frame motion estimation computation in H.264/AVC. ISCAS 2008: 632-635 - [c21]Yi-Ying Tsai, Chia-Jung Hsu, Chung-Ho Chen:
Address compression for scalable load/store queue implementation. ISCAS 2008: 1680-1683 - [c20]Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee:
A hybrid self-testing methodology of processor cores. ISCAS 2008: 3378-3381 - [c19]Yi-Ying Tsai, Chia-Jung Hsu, Chung-Ho Chen:
Power-efficient and scalable load/store queue design via address compression. SAC 2008: 1523-1527 - [c18]Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee:
A hybrid software-based self-testing methodology for embedded processor. SAC 2008: 1528-1534 - 2007
- [j15]Chung-Ho Chen, Min-Tsai Lai:
Determining the optimum process mean based on quadratic quality loss function and rectifying inspection plan. Eur. J. Oper. Res. 182(2): 755-763 (2007) - [j14]Chung-Ho Chen, Min-Tsai Lai:
Economic manufacturing quantity, optimum process mean, and economic specification limits setting under the rectifying inspection plan. Eur. J. Oper. Res. 183(1): 336-344 (2007) - [j13]Chung-Ming Chen, Chung-Ho Chen:
An Efficient Pipeline Architecture for Deblocking Filter in H.264/AVC. IEICE Trans. Inf. Syst. 90-D(1): 99-107 (2007) - [j12]Chung-Ho Chen, Kuo-Su Hsiao:
Scalable Dynamic Instruction Scheduler through Wake-Up Spatial Locality. IEEE Trans. Computers 56(11): 1534-1548 (2007) - [j11]Chung-Ho Chen, Chih-Kai Wei, Tai-Hua Lu, Hsun-Wei Gao:
Software-Based Self-Testing With Multiple-Level Abstractions for Soft Processor Cores. IEEE Trans. Very Large Scale Integr. Syst. 15(5): 505-517 (2007) - [c17]Wei-Cheng Lin, Chung-Ho Chen:
Reduction of Frame Memory Accesses and Motion Estimation Computations in MPEG Video Encoder. ICCCN 2007: 817-820 - [c16]Wei-Cheng Lin, Chung-Ho Chen:
A data-reuse scheme for avoiding unnecessary memory accesses in MPEG-4 ASP video decoder. SoCC 2007: 243-246 - 2006
- [j10]Chao-Yu Chou, Chun-Hua Chen, Chung-Ho Chen:
Economic design of variable sampling intervals T2 control charts using genetic algorithms. Expert Syst. Appl. 30(2): 233-242 (2006) - [j9]Chao-Yu Chou, Yu-Chang Lin, Chun-Lang Chang, Chung-Ho Chen:
On the bootstrap confidence intervals of the process incapability index Cpp. Reliab. Eng. Syst. Saf. 91(4): 452-459 (2006) - [j8]Kuo-Su Hsiao, Chung-Ho Chen:
Wake-Up Logic Optimizations Through Selective Match and Wakeup Range Limitation. IEEE Trans. Very Large Scale Integr. Syst. 14(10): 1089-1102 (2006) - [c15]Kuo-Su Hsiao, Chung-Ho Chen:
Improving Scalability and Complexity of Dynamic Scheduler through Wakeup-Based Scheduling. ICCD 2006: 197-202 - [c14]Wei-Cheng Lin, Chung-Ho Chen:
Exploring reusable frame buffer data for MPEG-4 video decoding. ISCAS 2006 - [c13]Chung-Ho Chen, Yi-Cheng Chung, Chen-Hua Wang, Han-Chiang Chen:
Design of a Giga-bit Hardware Accelerator for the iSCSI Initiator. LCN 2006: 257-263 - 2005
- [c12]Kuo-Su Hsiao, Chung-Ho Chen:
An efficient wakeup design for energy reduction in high-performance superscalar processors. Conf. Computing Frontiers 2005: 353-360 - [c11]Chung-Ming Chen, Chung-Ho Chen:
An Efficient Architecture for Deblocking Filter in H.264/AVC Video Coding. Computer Graphics and Imaging 2005: 177-181 - [c10]Chung-Ming Chen, Chung-Ho Chen:
An efficient VLSI architecture for edge filtering in H.264/AVC. Circuits, Signals, and Systems 2005: 118-122 - 2003
- [c9]Ning-Yaun Ker, Chung-Ho Chen:
An effective SDRAM power mode management scheme for performance and energy sensitive embedded systems. ASP-DAC 2003: 515-518 - 2001
- [j7]Ming-Der Shieh, Ming-Hwa Sheu, Chung-Ho Chen, Hsin-Fu Lo:
A Systematic Approach for Parallel CRC Computations. J. Inf. Sci. Eng. 17(3): 445-461 (2001) - [c8]Ming-Chih Chen, Ing-Jer Huang, Chung-Ho Chen:
Parameterized MAC unit implementation. ASP-DAC 2001: 23-24
1990 – 1999
- 1999
- [j6]Chung-Ho Chen, Arun K. Somani:
Fault Containment in Cache Memories for TMR Redundant Processor Systems. IEEE Trans. Computers 48(4): 386-397 (1999) - [j5]Chung-Ho Chen, Feng-Fu Lin:
An Easy-to-Use Approach for Practical Bus-Based System Design. IEEE Trans. Computers 48(8): 780-793 (1999) - 1997
- [c7]Chung-Ho Chen, Akida Wu:
Microarchitecture Support for Improving the Performance of Load Target Prediction. MICRO 1997: 228-234 - [c6]Chung-Ho Chen, Akida Wu:
An enhanced DLX-based superscalar system simulator. WCAE@HPCA 1997: 5 - 1996
- [j4]Chung-Ho Chen, Arun K. Somani:
Architecture Technique Trade-Offs Using Mean Memory Delay Time. IEEE Trans. Computers 45(10): 1089-1100 (1996) - [j3]Craig M. Wittenbrink, Arun K. Somani, Chung-Ho Chen:
Cache write generate for parallel image processing on shared memory architectures. IEEE Trans. Image Process. 5(7): 1204-1208 (1996) - 1995
- [j2]Robert M. Haralick, Arun K. Somani, Craig M. Wittenbrink, Robert Johnson, Kenneth Cooper, Linda G. Shapiro, Ihsin T. Phillips, Jenq-Neng Hwang, William Cheung, Yung Hsi Yao, Chung-Ho Chen, Larry Yang, Brian Daugherty, Bob Lorbeski, Kent Loving, Tom Miller, Larye Parkins, Steve Soos:
Proteus: A reconfigurable computational network for computer vision. Mach. Vis. Appl. 8(2): 85-100 (1995) - 1994
- [c5]Chung-Ho Chen, Arun K. Somani:
A Cache Protocol for Error Detection and Recovery in Fault-Tolerant Computing Systems. FTCS 1994: 278-287 - [c4]Chung-Ho Chen, Arun K. Somani:
A Unified Architectural Tradeoff Methodology. ISCA 1994: 348-357 - 1992
- [c3]Chung-Ho Chen, Arun K. Somani:
Effects of Cache Traffic on Shared Bus Multiprocessor Systems. ICPP (1) 1992: 285-288 - [c2]Robert M. Haralick, Arun K. Somani, Craig M. Wittenbrink, Robert Johnson, Kenneth Cooper, Linda G. Shapiro, Ihsin T. Phillips, Jenq-Neng Hwang, William Cheung, Yung Hsi Yao, Chung-Ho Chen, Larry Yang, Brian Daugherty, Bob Lorbeski, Kent Loving, Tom Miller, Larye Parkins, Steve Soos:
Proteus: a reconfigurable computational network for computer vision. ICPR (4) 1992: 43-54 - 1991
- [c1]Arun K. Somani, Craig M. Wittenbrink, Robert M. Haralick, Linda G. Shapiro, Jenq-Neng Hwang, Chung-Ho Chen, Robert Johnson, Kenneth Cooper:
Proteus System Architecture and Organization. IPPS 1991: 287-294
1980 – 1989
- 1982
- [j1]Chung-Ho Chen:
An Algebraic Model of Arithmetic Codes. IEEE Trans. Computers 31(4): 318-321 (1982)
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-04-25 05:48 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
