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Link to original content: https://dblp.dagstuhl.de/pid/235/0126.rss
dblp: Gangmin Cho https://dblp.org/pid/235/0126.html dblp person page RSS feed Tue, 01 Oct 2024 20:42:55 +0200 en-US daily 1 released under the CC0 1.0 license dblp@dagstuhl.de (dblp team) dblp@dagstuhl.de (dblp team) Computers/Computer_Science/Publications/Bibliographies http://www.rssboard.org/rss-specification https://dblp.org/img/logo.144x51.pngdblp: Gangmin Chohttps://dblp.org/pid/235/0126.html14451 Fast IR-Drop Prediction of Analog Circuits Using Recurrent Synchronized GCN and Y-Net Model.https://doi.org/10.23919/DATE58400.2024.10546845, , , , :
Fast IR-Drop Prediction of Analog Circuits Using Recurrent Synchronized GCN and Y-Net Model. DATE : 1-6]]>
https://dblp.org/rec/conf/date/LeeHJCS24Mon, 01 Jan 2024 00:00:00 +0100
Block-Level Power Net Routing of Analog Circuit Using Reinforcement Learning.https://doi.org/10.1109/ISCAS46773.2023.10181411, , :
Block-Level Power Net Routing of Analog Circuit Using Reinforcement Learning. ISCAS : 1-5]]>
https://dblp.org/rec/conf/iscas/KimCS23Sun, 01 Jan 2023 00:00:00 +0100
Routability-Driven Power Distribution Network Synthesis with IR-Drop Budgeting.https://doi.org/10.1109/MLCAD58807.2023.10299845, , , :
Routability-Driven Power Distribution Network Synthesis with IR-Drop Budgeting. MLCAD : 1-6]]>
https://dblp.org/rec/conf/mlcad/LeeCCS23Sun, 01 Jan 2023 00:00:00 +0100
Simultaneous Clock Wire Sizing and Shield Insertion for Minimizing Routing Blockage.https://doi.org/10.1109/MLCAD58807.2023.10299861, , , :
Simultaneous Clock Wire Sizing and Shield Insertion for Minimizing Routing Blockage. MLCAD : 1-6]]>
https://dblp.org/rec/conf/mlcad/SongCLS23Sun, 01 Jan 2023 00:00:00 +0100
Optimization of Machine Learning Guided Optical Proximity Correction.https://doi.org/10.1109/MWSCAS.2018.8623985, , :
Optimization of Machine Learning Guided Optical Proximity Correction. MWSCAS : 921-924]]>
https://dblp.org/rec/conf/mwscas/ChoCS18Mon, 01 Jan 2018 00:00:00 +0100