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ORCIDHiroyuki Ochi
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2020 – today
- 2023
[j26]Yuki Abe, Kazutoshi Kobayashi, Jun Shiomi, Hiroyuki Ochi:
Nonvolatile Storage Cells Using FiCC for IoT Processors with Intermittent Operations. IEICE Trans. Electron. 106(10): 546-555 (2023)- [j25]Ippei Tanaka, Naoyuki Miyagawa, Tomoya Kimura, Takashi Imagawa, Hiroyuki Ochi:
A CMOS-compatible Non-volatile Memory Element using Fishbone-in-cage Capacitor. IPSJ Trans. Syst. LSI Des. Methodol. 16: 35-44 (2023) - [c47]Xuanqi Li, Takashi Imagawa, Hiroyuki Ochi:
Finding All Solutions of Multi-terminal Numberlink Problem Utilizing Top-down ZDD Construction. ASICON 2023: 1-4 - [c46]Renya Makimoto, Takashi Imagawa, Hiroyuki Ochi:
Approximate Logarithmic Multipliers Using Half Compensation with Two Line Segments. SOCC 2023: 1-6 - 2022
- [c45]Yuki Abe, Kazutoshi Kobayashi, Jun Shiomi, Hiroyuki Ochi:
Zero-standby-power Nonvolatile Standard Cell Memory Using FiCC for IoT Processors with Intermittent Operations. COOL CHIPS 2022: 1-6 - [c44]Yuki Abe, Kazutoshi Kobayashi, Hiroyuki Ochi:
Nonvolatile Flip-Flops Using FiCC for IoT Processors with Intermittent Operations. MWSCAS 2022: 1-4 - 2021
- [c43]Takaki Urabe, Hiroyuki Ochi, Kazutoshi Kobayashi:
Nonvolatile SRAM Using Fishbone-in-Cage Capacitor in a 180 nm Standard CMOS Process for Zero-Standby and Instant-Powerup Embedded Memory on IoT. COOL CHIPS 2021: 1-3 - [c42]Takashi Imagawa, Jaehoon Yu, Masanori Hashimoto
, Hiroyuki Ochi:
MUX Granularity Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA. DATE 2021: 838-843 - 2020
- [c41]Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Yusuke Araki, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi, Kazutoshi Wakabayashi, Yukio Mitsuyama, Tadahiko Sugibayashi:
33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications. ISSCC 2020: 502-504
2010 – 2019
- 2018
- [j24]Hiroki Hihara, Akira Iwasaki, Masanori Hashimoto, Hiroyuki Ochi, Yukio Mitsuyama, Hidetoshi Onodera, Hiroyuki Kanbara, Kazutoshi Wakabayashi, Tadahiko Sugibayashi, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada, Makoto Miyamura, Toshitsugu Sakamoto:
Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture. IEEE Embed. Syst. Lett. 10(4): 119-122 (2018) - [j23]Hiroyuki Ochi, Kosei Yamaguchi, Tetsuaki Fujimoto, Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Takashi Imagawa, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Wataru Takahashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Jaehoon Yu, Masanori Hashimoto:
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2723-2736 (2018) - 2017
- [j22]Toshiki Higashi, Hiroyuki Ochi:
Area-Efficient LUT-Like Programmable Logic Using Atom Switch and Its Delay-Optimal Mapping Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(7): 1418-1426 (2017) - [c40]Takashi Imagawa, Koki Honda, Hiroyuki Ochi:
Placement algorithm for mixed-grained reconfigurable architecture with dedicated carry chain. SoCC 2017: 80-85 - [c39]Ryosuke Koike, Takashi Imagawa, Roberto Yusi Omaki, Hiroyuki Ochi:
Selectable grained reconfigurable architecture (SGRA) and its design automation. SoCC 2017: 196-201 - 2016
- [j21]Takashi Kishimoto, Wataru Takahashi, Kazutoshi Wakabayashi, Hiroyuki Ochi:
Range Limiter Using Connection Bounding Box for SA-Based Placement of Mixed-Grained Reconfigurable Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2328-2334 (2016) - [c38]Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto:
A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch. FPL 2016: 1-4 - 2015
- [j20]Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato:
An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs. IEICE Trans. Electron. 98-C(7): 741-750 (2015) - [c37]Masanori Hashimoto, Dawood Alnajiar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Takao Onoye, Hidetoshi Onodera:
Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis. ASP-DAC 2015: 14-15 - [c36]Tomoya Kimura, Hiroyuki Ochi:
A -0.5V-input voltage booster circuit for on-chip solar cells in 0.18µm CMOS technology. ISCIT 2015: 193-196 - [c35]Toshiki Higashi, Hiroyuki Ochi:
Area-efficient LUT-like programmable logic using atom switch and its mapping algorithm. ISCIT 2015: 201-204 - 2014
- [j19]Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye, Hidetoshi Onodera:
Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2518-2529 (2014) - [c34]Takashi Sato, Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi:
Experimental validation of minimum operating-voltage-estimation for low supply voltage circuits. ISQED 2014: 428-433 - 2013
- [j18]Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis. IEICE Trans. Electron. 96-C(4): 454-462 (2013) - [j17]Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element. IEICE Trans. Electron. 96-C(4): 473-481 (2013) - [c33]Tetsuro Miyakawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
Realization of frequency-domain circuit analysis through random walk. ASP-DAC 2013: 169-174 - [c32]Zoltán Endre Rákossy, Masayuki Hiromoto, Hiroshi Tsutsui, Takashi Sato, Yukihiro Nakamura, Hiroyuki Ochi:
Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array. DATE 2013: 535-540 - [c31]Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
A cost-effective selective TMR for heterogeneous coarse-grained reconfigurable architectures based on DFG-level vulnerability analysis. DATE 2013: 701-706 - [c30]Takumi Morishita, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
Fast and memory-efficient GPU implementations of krylov subspace methods for efficient power grid analysis. ACM Great Lakes Symposium on VLSI 2013: 95-100 - [c29]Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
High-speed DFG-level SEU vulnerability analysis for applying selective TMR to resource-constrained CGRA. ISQED 2013: 538-545 - [c28]Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
Multi-trap RTN parameter extraction based on Bayesian inference. ISQED 2013: 597-602 - [c27]Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye:
Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design. ReConFig 2013: 1-6 - [c26]Hiroyuki Ochi, Toshihiko Ota, Ataru Yamaoka, Hiromasa Watanabe, Yohei Kondo, Nobuyuki Tokuda, Hiroyuki Taguchi, Taketoshi Matsumoto, Tomoki Akai, Hikaru Kobayashi, Shigeki Imai:
Sealed mask ROM wafer with 5 mm magnetic resonant coupling for long-term digital data preservation. SoCC 2013: 262-266 - 2012
- [j16]Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2242-2250 (2012) - [j15]Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
Bayesian Estimation of Multi-Trap RTN Parameters Using Markov Chain Monte Carlo Method. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2272-2283 (2012) - [j14]Hiroshi Tsutsui, Koichi Hattori, Hiroyuki Ochi, Yukihiro Nakamura:
A high-throughput pipelined parallel architecture for JPEG XR encoding. ACM Trans. Embed. Comput. Syst. 11(4): 72:1-72:25 (2012) - [c25]Takashi Sato, Hiromitsu Awano, Hirofttmi Shimizu, Hiroshi Tsutsui, Hiroyuki Ochi:
Statistical observations of NBTI-induced threshold voltage shifts on small channel-area devices. ISQED 2012: 306-311 - 2011
- [c24]Tetsuro Miyakawa, Koh Yamanaga, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
Acceleration of random-walk-based linear circuit analysis using importance sampling. ACM Great Lakes Symposium on VLSI 2011: 211-216 - [c23]Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
A fully pipelined implementation of Monte Carlo based SSTA on FPGAs. ISQED 2011: 785-790 - [c22]Junya Kawashima, Hiroyuki Ochi, Hiroshi Tsutsui, Takashi Sato:
A design strategy for sub-threshold circuits considering energy-minimization and yield-maximization. SoCC 2011: 57-62 - 2010
- [j13]Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato:
Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2524-2532 (2010) - [c21]Kentaro Katayama, Shiho Hagiwara, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
Sequential importance sampling for low-probability and high-dimensional SRAM yield analysis. ICCAD 2010: 703-708 - [c20]Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato:
Scan based process parameter estimation through path-delay inequalities. ISCAS 2010: 3553-3556 - [c19]Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato:
A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation. SoCC 2010: 248-253 - [c18]Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato:
Path clustering for adaptive test. VTS 2010: 15-20
2000 – 2009
- 2009
- [j12]Hiroki Sugano, Takahiko Masuzaki, Hiroshi Tsutsui, Takao Onoye, Hiroyuki Ochi, Yukihiro Nakamura:
Efficient Memory Organization Framework for JPEG2000 Entropy Codec. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(8): 1970-1977 (2009) - [j11]Hiroki Sugano, Hiroyuki Ochi, Yukihiro Nakamura, Ryusuke Miyamoto:
Hardware Accelerator for Run-Time Learning Adopted in Object Recognition with Cascade Particle Filter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(11): 2801-2808 (2009) - [j10]Masayuki Hiromoto, Hiroyuki Ochi, Yukihiro Nakamura:
An Asynchronous IEEE-754-standard Single-precision Floating-point Divider for FPGA. Inf. Media Technol. 4(2): 250-260 (2009) - [j9]Masayuki Hiromoto, Hiroyuki Ochi, Yukihiro Nakamura:
An Asynchronous IEEE-754-standard Single-precision Floating-point Divider for FPGA. IPSJ Trans. Syst. LSI Des. Methodol. 2: 103-113 (2009) - [c17]Koichi Hattori, Hiroshi Tsutsui, Hiroyuki Ochi, Yukihiro Nakamura:
A high-throughput pipelined architecture for JPEG XR encoding. ESTIMedia 2009: 9-17 - [c16]Dawood Alnajiar, Younghun Ko, Takashi Imagawa, Hiroaki Konoura, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi, Takao Onoye:
Coarse-grained dynamically reconfigurable architecture with flexible reliability. FPL 2009: 186-192 - [c15]Zoltan Endre Rakosi, Masayuki Hiromoto, Hiroyuki Ochi, Yukihiro Nakamura:
Hot-Swapping architecture extension for mitigation of permanent functional unit faults. FPL 2009: 578-581 - [c14]Ryoji Kadota, Hiroki Sugano, Masayuki Hiromoto, Hiroyuki Ochi, Ryusuke Miyamoto, Yukihiro Nakamura:
Hardware Architecture for HOG Feature Extraction. IIH-MSP 2009: 1330-1333 - [c13]Masayuki Hiromoto, Hiroshi Tsutsui, Hiroyuki Ochi, Tomoyuki Osano, Norihiro Ishikawa, Yukihiro Nakamura:
Dynamic rate control for media streaming in high-speed mobile networks. WCNC 2009: 2983-2988 - 2008
- [j8]Kentaro Nakahara, Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura:
Autonomous Repair Fault Tolerant Dynamic Reconfigurable Device. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3612-3621 (2008) - [c12]Koichi Hattori, Hiroshi Tsutsui, Hiroyuki Ochi, Yukihiro Nakamura:
An architecture of photo core transform in HD photo coding system for embedded systems of various bandwidths. APCCAS 2008: 1592-1595 - 2007
- [j7]Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura:
A Simulation Platform for Designing Cell-Array-Based Self-Reconfigurable Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(4): 784-791 (2007) - [j6]Takahiro Murooka, Akira Nagoya, Toshiaki Miyazaki, Hiroyuki Ochi, Yukihiro Nakamura:
Network Processor for High-Speed Network and Quick Programming. J. Circuits Syst. Comput. 16(1): 65-79 (2007) - [c11]Norihiro Ishikawa, Hiroshi Tsutsui, Jaehoon Yu, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura, Takaaki Komura, Yoshitaka Uchida:
Implementation of AV Streaming System Using Peer-to-Peer Communication. CCNC 2007: 778-782 - [c10]Hiromitsu Sumino, Norihiro Ishikawa, Hiroshi Tsutsui, Hiroyuki Ochi, Yukihiro Nakamura, Yoshitaka Uchida:
Home Appliance Control from Mobile Phones. CCNC 2007: 793-797 - 2006
- [j5]Hiroyuki Ochi, Shigeaki Tagashira, Satoshi Fujita:
A Localization Scheme for Sensor Networks Based on Wireless Communication with Anchor Groups. IEICE Trans. Inf. Syst. 89-D(5): 1614-1621 (2006) - [j4]Kentaro Nakahara, Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura:
Fault Tolerant Dynamic Reconfigurable Device Based on EDAC with Rollback. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3652-3658 (2006) - [c9]Kentaro Nakahara, Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura:
Autonomous-repair cell for fault tolerant dynamic-reconfigurable devices. FPGA 2006: 224 - [c8]Kentaro Nakahara, Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura:
Fault Tolerant Reconfigurable Device Based on Autonomous-Repair Cells. FPL 2006: 1-6 - [c7]Hiroki Sugano, Hiroshi Tsutsui, Takahiko Masuzaki, Takao Onoye, Hiroyuki Ochi, Yukihiro Nakamura:
Efficient memory architecture for JPEG2000 entropy codec. ISCAS 2006 - [c6]Ryusuke Miyamoto, Hiroki Sugano, Hiroaki Saito, Hiroshi Tsutsui, Hiroyuki Ochi, Ken'ichi Hatanaka, Yukihiro Nakamura:
Pedestrian Recognition in Far-Infrared Images by Combining Boosting-Based Detection and Skeleton-Based Stochastic Tracking. PSIVT 2006: 483-494 - 2005
- [j3]Tomonori Izumi, Shin'ichi Kouyama, Hiroyuki Ochi, Yukihiro Nakamura:
An Integrated Approach of Variable Ordering and Logic Mapping into LUT-Array-Based PLD. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(4): 907-914 (2005) - [c5]Hiroyuki Ochi, Shigeaki Tagashira, Satoshi Fujita:
A Localization Scheme for Sensor Networks based onWireless Communication with Anchor Groups. ICPADS (1) 2005: 299-305 - 2003
- [j2]Hiroyuki Ochi, Tatsuya Suzuki, Sayaka Matsunaga, Yoichi Kawano, Takao Tsuda:
Development of an IP Library of IEEE-754-Standard Single-Precision Floating-Point Dividers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3020-3027 (2003) - 2002
- [j1]Takahiro Kakimoto, Hiroyuki Ochi, Takao Tsuda:
Datapath-Layout-Driven Design for Low-Power Standard-Cell LSI Implementation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2795-2798 (2002) - 2000
- [c4]Hirofumi Sakamoto, Ken'ichiro Uda, Bu-Yeol Lee, Hiroyuki Ochi, Kazuo Taki, Takao Tsuda:
A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL. ASP-DAC 2000: 33-34
1990 – 1999
- 1993
- [c3]Hiroyuki Ochi, Koichi Yasuoka, Shuzo Yajima:
Breadth-first manipulation of very large binary-decision diagrams. ICCAD 1993: 48-55 - 1991
- [c2]Hiromi Hiraishi, Kiyoharu Hamaguchi, Hiroyuki Ochi, Shuzo Yajima:
Vectorized Symbolic Model Checking of Computation Tree Logic for Sequential Machine Verification. CAV 1991: 214-224 - [c1]Hiroyuki Ochi, Nagisa Ishiura, Shuzo Yajima:
Breadth-First Manipulation of SBDD of Boolean Functions for Vector Processing. DAC 1991: 413-416
Coauthor Index
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