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ORCIDSergio López-Buedo
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2020 – today
- 2023
[j14]Tobias Alonso
, Gustavo Sutter, Sergio López-Buedo, Jorge E. López de Vergara:
Enhancing Conditional Stalling to Boost Performance of Stream-Processing Logic With RAW Dependencies. IEEE Trans. Circuits Syst. II Express Briefs 70(7): 2620-2624 (2023)- 2022
- [j13]Behnam Shariati, Luis Velasco, Jose-Juan Pedreno-Manresa, Annika Dochhan, Ramon Casellas, Abubakar Siddique Muqaddas, Óscar González de Dios, Lourdes Luque Canto, Bodo Lent, Jorge E. López de Vergara, Sergio López-Buedo, Francisco-Javier Moreno-Muro, Pablo Pavón, Marc Ruiz, Sai Kireet Patri, Alessio Giorgetti, Filippo Cugini, Andrea Sgambelluri, Reza Nejabati, Dimitra Simeonidou, Ralf-Peter Braun, Achim Autenrieth, Jörg-Peter Elbers, Johannes K. Fischer, Ronald Freund:
Demonstration of latency-aware 5G network slicing on optical metro networks. JOCN 14(1): A81-A90 (2022) - [i3]Behnam Shariati, Luis Velasco, Jose-Juan Pedreno-Manresa, Annika Dochhan, Ramon Casellas, Abubakar Siddique Muqaddas, Óscar González de Dios, Lourdes Luque Canto, Bodo Lent, Jorge E. López de Vergara, Sergio López-Buedo, Francisco Javier Moreno, Pablo Pavón, Marc Ruiz, Sai Kireet Patri, Alessio Giorgetti, Filippo Cugini, Andrea Sgambelluri, Reza Nejabati, Dimitra Simeonidou, Ralf-Peter Braun, Achim Autenrieth, Jörg-Peter Elbers, Johannes K. Fischer, Ronald Freund:
Demonstration of latency-aware 5G network slicing on optical metro networks. CoRR abs/2202.10118 (2022) - 2021
- [c34]Behnam Shariati, Jose-Juan Pedreno-Manresa, Annika Dochhan, Abubakar Siddique Muqaddas, Ramon Casellas, Óscar González de Dios, Lourdes Luque Canto, Bodo Lent, Jorge E. López de Vergara, Sergio López-Buedo, Francisco Javier Moreno, Pablo Pavón, Luis Velasco, Sai Kireet Patri, Alessio Giorgetti, Filippo Cugini, Andrea Sgambelluri, Reza Nejabati, Dimitra Simeonidou, Ralf-Peter Braun, Achim Autenrieth, Jörg-Peter Elbers, Johannes Karl Fischer, Ronald Freund:
A Latency-Aware Real-Time Video Surveillance Demo: Network Slicing for Improving Public Safety. OFC 2021: 1-3 - [i2]Behnam Shariati, Jose-Juan Pedreno-Manresa, Annika Dochhan, Abubakar Siddique Muqaddas, Ramon Casellas, Óscar González de Dios, Lourdes Luque Canto, Bodo Lent, Jorge E. López de Vergara, Sergio López-Buedo, Francisco Javier Moreno, Pablo Pavón, Luis Velasco, Sai Kireet Patri, Alessio Giorgetti, Filippo Cugini, Andrea Sgambelluri, Reza Nejabati, Dimitra Simeonidou, Ralf-Peter Braun, Achim Autenrieth, Jörg-Peter Elbers, Johannes Karl Fischer, Ronald Freund:
A Latency-Aware Real-Time Video Surveillance Demo: Network Slicing for Improving Public Safety. CoRR abs/2107.02505 (2021)
2010 – 2019
- 2019
- [c33]Mario Ruiz, David Sidler, Gustavo Sutter, Gustavo Alonso, Sergio López-Buedo:
Limago: An FPGA-Based Open-Source 100 GbE TCP/IP Stack. FPL 2019: 286-292 - 2018
- [c32]Maciej Bielski, Ilias Syrigos, Kostas Katrinis, Dimitris Syrivelis, Andrea Reale, Dimitris Theodoropoulos, Nikolaos Alachiotis, Dionisis N. Pnevmatikatos, E. H. Pap, George Zervas, Vaibhawa Mishra, Arsalan Saljoghei, Alvise Rigo, Jose Fernando Zazo, Sergio López-Buedo, Martí Torrents, Ferad Zyulkyarov, Michael Enrico, Óscar González de Dios:
dReDBox: Materializing a full-stack rack-scale system prototype of a next-generation disaggregated datacenter. DATE 2018: 1093-1098 - [c31]Gustavo Sutter, Mario Ruiz, Sergio López-Buedo, Gustavo Alonso:
FPGA-based TCP/IP Checksum Offloading Engine for 100 Gbps Networks. ReConFig 2018: 1-6 - [c30]Rolf Neugebauer, Gianni Antichi, José Fernando Zazo, Yury Audzevich, Sergio López-Buedo, Andrew W. Moore:
Understanding PCIe performance for end host networking. SIGCOMM 2018: 327-341 - 2017
- [c29]Carlos Vega, Jose Fernando Zazo, Hugo Meyer, Ferad Zyulkyarov, Sergio López-Buedo, Javier Aracil:
Diluting the Scalability Boundaries: Exploring the Use of Disaggregated Architectures for High-Level Network Data Analysis. HPCC/SmartCity/DSS 2017: 340-347 - [c28]Mario Ruiz, Gustavo Sutter, Sergio López-Buedo, Jose Fernando Zazo, Jorge E. López de Vergara:
An FPGA-based approach for packet deduplication in 100 gigabit-per-second networks. ReConFig 2017: 1-6 - [c27]Jose Fernando Zazo, Sergio López-Buedo, Mario Ruiz, Gustavo Sutter:
A single-FPGA architecture for detecting heavy hitters in 100 Gbit/s ethernet links. ReConFig 2017: 1-6 - [i1]Carlos Vega, Jose Fernando Zazo, Hugo Meyer, Ferad Zyulkyarov, Sergio López-Buedo, Javier Aracil:
Diluting the Scalability Boundaries: Exploring the Use of Disaggregated Architectures for High-Level Network Data Analysis. CoRR abs/1709.06127 (2017) - 2016
- [j12]Mario Ruiz, Javier Ramos, Gustavo Sutter, Jorge E. López de Vergara, Sergio López-Buedo, Javier Aracil:
Accurate and affordable packet-train testing systems for multi-gigabit-per-second networks. IEEE Commun. Mag. 54(3): 80-87 (2016) - [c26]Kostas Katrinis, Dimitris Syrivelis, Dionisios N. Pnevmatikatos, Georgios Zervas, Dimitris Theodoropoulos, Iordanis Koutsopoulos, K. Hasharoni, Daniel Raho, Christian Pinto, Felix Espina, Sergio López-Buedo, Qianqiao Chen, Mario Nemirovsky, Damian Roca, H. Klos, T. Berends:
Rack-scale disaggregated cloud data centers: The dReDBox project vision. DATE 2016: 690-695 - [c25]Kostas Katrinis, Georgios Zervas, Dionisios N. Pnevmatikatos, Dimitris Syrivelis, Theoni Alexoudi, Dimitris Theodoropoulos, Daniel Raho, Christian Pinto, Felix Espina, Sergio López-Buedo, Qianqiao Chen, Mario Nemirovsky, Damian Roca, H. Klos, T. Berends:
On interconnecting and orchestrating components in disaggregated data centers: The dReDBox project vision. EuCNC 2016: 235-239 - [c24]Mario Ruiz, Javier Ramos, Gustavo Sutter, Sergio López-Buedo, Jorge E. López de Vergara, C. Sisterna:
Harnessing Programmable SoCs to develop cost-effective network quality monitoring devices. FPL 2016: 1-4 - [c23]Mario Ruiz, Gustavo Sutter, Sergio López-Buedo, Jorge E. López de Vergara:
FPGA-based encrypted network traffic identification at 100 Gbit/s. ReConFig 2016: 1-6 - [c22]Jose Fernando Zazo, Sergio López-Buedo, Gustavo Sutter, Javier Aracil:
Automated synthesis of FPGA-based packet filters for 100 Gbps network monitoring applications. ReConFig 2016: 1-6 - 2015
- [c21]Mario Ruiz, Gustavo Sutter, Sergio López-Buedo, Javier Ramos, Jorge E. López de Vergara, Javier Aracil:
Leveraging open source platforms and high-level synthesis for the design of FPGA-based 10 GbE active network probes. ReConFig 2015: 1-6 - [c20]Jose Fernando Zazo, Sergio López-Buedo, Yury Audzevich, Andrew W. Moore:
A PCIe DMA engine to support the virtualization of 40 Gbps FPGA-accelerated network appliances. ReConFig 2015: 1-6 - 2014
- [j11]Marco Forconesi, Gustavo Sutter, Sergio López-Buedo, Jorge E. López de Vergara, Javier Aracil:
Bridging the gap between hardware and software open source network developments. IEEE Netw. 28(5): 13-19 (2014) - [c19]Jose Fernando Zazo, Marco Forconesi, Sergio López-Buedo, Gustavo Sutter, Javier Aracil:
TNT10G: A high-accuracy 10 GbE traffic player and recorder for multi-Terabyte traces. ReConFig 2014: 1-6 - 2013
- [j10]Diego Sanchez-Roman, Victor Moreno, Sergio López-Buedo, Gustavo Sutter, Iván González, Francisco J. Gomez-Arribas, Javier Aracil:
FPGA acceleration using high-level languages of a Monte-Carlo method for pricing complex options. J. Syst. Archit. 59(3): 135-143 (2013) - [c18]Raul Muñoz, Víctor López, Ramon Casellas, Óscar González de Dios, Filippo Cugini, Nicola Sambo, Antonio D'Errico, Ori Gerstel, Daniel King, Sergio López-Buedo, Patricia Layec, Antonio Cimmino, Ricardo Martínez, Roberto Morro:
IDEALIST control and service management solutions for dynamic and adaptive flexi-grid DWDM networks. Future Network & Mobile Summit 2013: 1-10 - [c17]Marco Forconesi, Gustavo Sutter, Sergio López-Buedo, Javier Aracil:
Accurate and flexible flow-based monitoring for high-speed networks. FPL 2013: 1-4 - 2012
- [j9]Esam El-Araby, Iván González, Sergio López-Buedo, Tarek A. El-Ghazawi:
A Convolve-And-MErge Approach for Exact Computations on High-Performance Reconfigurable Computers. Int. J. Reconfigurable Comput. 2012: 925864:1-925864:14 (2012) - [j8]Iván González, Sergio López-Buedo, Gustavo Sutter, Diego Sanchez-Roman, Francisco J. Gomez-Arribas, Javier Aracil:
Virtualization of reconfigurable coprocessors in HPRC systems with multicore architecture. J. Syst. Archit. 58(6-7): 247-256 (2012) - [c16]Jaime J. Garnica, Sergio López-Buedo, Víctor López, Javier Aracil, José María Gómez Hidalgo:
A FPGA-based scalable architecture for URL legal filtering in 100GbE networks. ReConFig 2012: 1-6 - 2011
- [j7]José Luis García-Dorado, José Alberto Hernández, Javier Aracil, Jorge E. López de Vergara, Sergio López-Buedo:
Characterization of the busy-hour traffic of IP networks based on their intrinsic features. Comput. Networks 55(9): 2111-2125 (2011) - [j6]Diego Sanchez-Roman, Gustavo Sutter, Sergio López-Buedo, Iván González, Francisco J. Gomez-Arribas, Javier Aracil, Francisco Palacios:
High-Level Languages and Floating-Point Arithmetic for FPGA-Based CFD Simulations. IEEE Des. Test Comput. 28(4): 28-37 (2011) - [c15]Victor Moreno, Jaime J. Garnica, Francisco J. Gomez-Arribas, Sergio López-Buedo, Iván González, Javier Aracil, Mikel Izal, Eduardo Magaña, Daniel Morató:
High-accuracy network monitoring using ETOMIC testbed. NGI 2011: 1-2
2000 – 2009
- 2008
- [j5]Iván González, Sergio López-Buedo, Francisco J. Gomez-Arribas:
Implementation of secure applications in self-reconfigurable systems. Microprocess. Microsystems 32(1): 23-32 (2008) - [j4]Proshanta Saha, Esam El-Araby, Miaoqing Huang, Mohamed Taher, Sergio López-Buedo, Tarek A. El-Ghazawi, Chang Shu, Kris Gaj, Alan Michalski, Duncan A. Buell:
Portable library development for reconfigurable computing systems: A case study. Parallel Comput. 34(4-5): 245-260 (2008) - [c14]Miaoqing Huang, Iván González, Sergio López-Buedo, Tarek A. El-Ghazawi:
A Framework to Improve IP Portability on Reconfigurable Computers. ERSA 2008: 191-197 - 2007
- [j3]Iván González, Estanislao Aguayo, Sergio López-Buedo:
Self-Reconfigurable Embedded Systems on Low-Cost FPGAs. IEEE Micro 27(4): 49-57 (2007) - [c13]José Luis García-Dorado, Javier Aracil, José Alberto Hernández, Sergio López-Buedo, Jorge E. López de Vergara, Pedro Reviriego, Gabriel Huecas, Santiago Pavón, Juan Quemada:
A Quality of Service Assessment Technique for Large-Scale Management of Multimedia Flows. MMNS 2007: 173-176 - 2006
- [c12]Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton, Sergio López-Buedo:
Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs. FCCM 2006: 35-44 - 2005
- [c11]Iván González, Francisco J. Gomez-Arribas, Sergio López-Buedo:
Hardware-Accelerated SSH on Self-Reconfigurable Systems. FPT 2005: 289-290 - 2004
- [c10]Sergio López-Buedo, Eduardo I. Boemo:
Making visible the thermal behaviour of embedded microprocessors on FPGAs: a progress report. FPGA 2004: 79-86 - 2003
- [c9]Iván González, Sergio López-Buedo, Francisco J. Gómez, Javier Martínez:
Using Partial Reconfiguration in Cryptographic Applications: An Implementation of the IDEA Algorithm. FPL 2003: 194-203 - 2002
- [c8]Sergio López-Buedo, Paula Riviere, Pablo Pernas, Eduardo I. Boemo:
Run-Time Reconfiguration to Check Temperature in Custom Computers: An Application of JBits Technology. FPL 2002: 162-170 - [c7]Elias Todorovich, M. Gilabert, Gustavo Sutter, Sergio López-Buedo, Eduardo I. Boemo:
A Tool for Activity Estimation in FPGAs. FPL 2002: 340-349 - [c6]Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo:
FSM Decomposition for Low Power in FPGA. FPL 2002: 350-359 - [c5]Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo:
Low-Power FSMs in FPGA: Encoding Alternatives. PATMOS 2002: 363-370 - 2000
- [j2]Sergio López-Buedo, Javier Garrido Salas, Eduardo I. Boemo:
Thermal Testing on Reconfigurable Computers. IEEE Des. Test Comput. 17(1): 84-91 (2000) - [c4]Luis Fernando Lago-Fernández, Manuel A. Sánchez-Montañés, Sergio López-Buedo:
A biologically inspired autonomous robot that learns approach-avoidance behaviors. Agents 2000: 27-28
1990 – 1999
- 1998
- [j1]Eduardo I. Boemo, Sergio López-Buedo, Juan M. Meneses:
Some experiments about wave pipelining on FPGA's. IEEE Trans. Very Large Scale Integr. Syst. 6(2): 232-237 (1998) - 1997
- [c3]Eduardo I. Boemo, Sergio López-Buedo:
Thermal monitoring on FPGAs using ring-oscillators. FPL 1997: 69-78 - 1996
- [c2]Eduardo I. Boemo, Sergio López-Buedo, Juan M. Meneses:
The Wave Pipeline Effect on LUT-Based FPGA Architectures. FPGA 1996: 45-50 - 1995
- [c1]Eduardo I. Boemo, Guillermo González de Rivera, Sergio López-Buedo, Juan M. Meneses:
Some Notes on Power Management on FPGA-Based Systems. FPL 1995: 149-157
Coauthor Index
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