{"id":"https://openalex.org/W2008369726","doi":"https://doi.org/10.1145/1837274.1837431","title":"Network on chip design and optimization using specialized influence models","display_name":"Network on chip design and optimization using specialized influence models","publication_year":2010,"publication_date":"2010-06-13","ids":{"openalex":"https://openalex.org/W2008369726","doi":"https://doi.org/10.1145/1837274.1837431","mag":"2008369726"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1145/1837274.1837431","pdf_url":null,"source":{"id":"https://openalex.org/S4363608921","display_name":"Proceedings of the 34th Design Automation Conference","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5086561910","display_name":"Cristinel Ababei","orcid":"https://orcid.org/0000-0002-7609-5304"},"institutions":[{"id":"https://openalex.org/I57328836","display_name":"North Dakota State University","ror":"https://ror.org/05h1bnb22","country_code":"US","type":"education","lineage":["https://openalex.org/I57328836"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Cristinel Ababei","raw_affiliation_strings":["Electrical and Computer Engineering Department North Dakota State University, Fargo, ND 58108"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department North Dakota State University, Fargo, ND 58108","institution_ids":["https://openalex.org/I57328836"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5086561910"],"corresponding_institution_ids":["https://openalex.org/I57328836"],"apc_list":null,"apc_paid":null,"fwci":0.535,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":2,"citation_normalized_percentile":{"value":0.393907,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":71,"max":75},"biblio":{"volume":"200","issue":null,"first_page":"625","last_page":"626"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9983,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9979,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/networks-on-chip","display_name":"Networks on Chip","score":0.596382},{"id":"https://openalex.org/keywords/noc-architecture","display_name":"NoC Architecture","score":0.536779},{"id":"https://openalex.org/keywords/power-optimization","display_name":"Power Optimization","score":0.532617},{"id":"https://openalex.org/keywords/cmos-design","display_name":"CMOS Design","score":0.518765},{"id":"https://openalex.org/keywords/frequency-scaling","display_name":"Frequency scaling","score":0.515785},{"id":"https://openalex.org/keywords/system-on-chip","display_name":"System-on-Chip","score":0.508133},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.43061775}],"concepts":[{"id":"https://openalex.org/C2780801425","wikidata":"https://www.wikidata.org/wiki/Q5164392","display_name":"Construct (python library)","level":2,"score":0.8156258},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7962066},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.60700905},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5205584},{"id":"https://openalex.org/C157742956","wikidata":"https://www.wikidata.org/wiki/Q3237776","display_name":"Frequency scaling","level":3,"score":0.515785},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.48408356},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.4704572},{"id":"https://openalex.org/C28719098","wikidata":"https://www.wikidata.org/wiki/Q44946","display_name":"Point (geometry)","level":2,"score":0.44009158},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.43061775},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.41195688},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.32880363},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.21550405},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.14321345},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1173628},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1145/1837274.1837431","pdf_url":null,"source":{"id":"https://openalex.org/S4363608921","display_name":"Proceedings of the 34th Design Automation Conference","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[],"grants":[],"datasets":[],"versions":[],"referenced_works_count":6,"referenced_works":["https://openalex.org/W1975993564","https://openalex.org/W2097264805","https://openalex.org/W2135933214","https://openalex.org/W2141100290","https://openalex.org/W2142325999","https://openalex.org/W2170954333"],"related_works":["https://openalex.org/W4863605","https://openalex.org/W4362544990","https://openalex.org/W2754086592","https://openalex.org/W2388672758","https://openalex.org/W2293773707","https://openalex.org/W2144357574","https://openalex.org/W2135981148","https://openalex.org/W2096946389","https://openalex.org/W2065289416","https://openalex.org/W1978899622"],"abstract_inverted_index":{"In":[0],"this":[1,50],"study,":[2],"we":[3,48],"propose":[4],"the":[5,13,33,70],"use":[6,49],"of":[7,16,37,69,88],"specialized":[8],"influence":[9],"models":[10,83],"to":[11,23,52],"capture":[12],"dynamic":[14,58],"behavior":[15],"a":[17,25,54],"Network-on-Chip":[18],"(NoC).":[19],"Our":[20],"goal":[21],"is":[22],"construct":[24,53],"versatile":[26],"modeling":[27],"framework":[28,51],"that":[29,76],"will":[30],"help":[31],"in":[32],"development":[34],"and":[35,39,60,86],"analysis":[36],"distributed":[38],"adaptive":[40],"features":[41],"for":[42,57,84],"NoCs.":[43,89],"As":[44],"an":[45],"application":[46],"testbench,":[47],"design":[55],"methodology":[56],"voltage":[59],"frequency":[61],"scaling":[62],"(DVFS).":[63],"We":[64],"also":[65],"point":[66],"out":[67],"similarities":[68],"proposed":[71],"model":[72],"with":[73],"backpressure":[74],"mechanisms":[75],"could":[77],"be":[78],"potentially":[79],"exploited":[80],"toward":[81],"enhanced":[82],"estimation":[85],"optimization":[87]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2008369726","counts_by_year":[{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2024-12-05T03:10:55.522466","created_date":"2016-06-24"}