{"id":"https://openalex.org/W1990050178","doi":"https://doi.org/10.1109/rsp.2014.6966895","title":"System-on-chip processor using different FPGA architectures in the VTR CAD flow","display_name":"System-on-chip processor using different FPGA architectures in the VTR CAD flow","publication_year":2014,"publication_date":"2014-10-01","ids":{"openalex":"https://openalex.org/W1990050178","doi":"https://doi.org/10.1109/rsp.2014.6966895","mag":"1990050178"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/rsp.2014.6966895","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102839133","display_name":"Jingjing Li","orcid":"https://orcid.org/0000-0001-6631-0763"},"institutions":[{"id":"https://openalex.org/I106938459","display_name":"University of New Brunswick","ror":"https://ror.org/05nkf0n29","country_code":"CA","type":"education","lineage":["https://openalex.org/I106938459"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Jingjing Li","raw_affiliation_strings":["Faculty of Computer Science University of New Brunswick Fredericton Canada"],"affiliations":[{"raw_affiliation_string":"Faculty of Computer Science University of New Brunswick Fredericton Canada","institution_ids":["https://openalex.org/I106938459"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076884555","display_name":"Konstantin Nasartschuk","orcid":null},"institutions":[{"id":"https://openalex.org/I106938459","display_name":"University of New Brunswick","ror":"https://ror.org/05nkf0n29","country_code":"CA","type":"education","lineage":["https://openalex.org/I106938459"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Konstantin Nasartschuk","raw_affiliation_strings":["Faculty of Computer Science University of New Brunswick Fredericton Canada"],"affiliations":[{"raw_affiliation_string":"Faculty of Computer Science University of New Brunswick Fredericton Canada","institution_ids":["https://openalex.org/I106938459"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5067605823","display_name":"Kenneth B. Kent","orcid":"https://orcid.org/0000-0003-2764-823X"},"institutions":[{"id":"https://openalex.org/I106938459","display_name":"University of New Brunswick","ror":"https://ror.org/05nkf0n29","country_code":"CA","type":"education","lineage":["https://openalex.org/I106938459"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Kenneth Kent","raw_affiliation_strings":["Faculty of Computer Science University of New Brunswick Fredericton Canada"],"affiliations":[{"raw_affiliation_string":"Faculty of Computer Science University of New Brunswick Fredericton Canada","institution_ids":["https://openalex.org/I106938459"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.994,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":3,"citation_normalized_percentile":{"value":0.646817,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":76,"max":79},"biblio":{"volume":"15","issue":null,"first_page":"72","last_page":"77"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.764755},{"id":"https://openalex.org/keywords/fpga","display_name":"FPGA","score":0.57004},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5445464},{"id":"https://openalex.org/keywords/system-on-chip","display_name":"System-on-Chip","score":0.512191},{"id":"https://openalex.org/keywords/multi-core-processors","display_name":"Multi-core Processors","score":0.510885},{"id":"https://openalex.org/keywords/routing-algorithms","display_name":"Routing Algorithms","score":0.505633},{"id":"https://openalex.org/keywords/dataflow-programming-languages","display_name":"Dataflow Programming Languages","score":0.501814},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.49067843},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.4772482},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.41751197}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.85258526},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.764755},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.7599863},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.749943},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.60252804},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5901872},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5753718},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5445464},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.51811594},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5033588},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.49067843},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.4772482},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.41751197},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/rsp.2014.6966895","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.46,"display_name":"Affordable and clean energy"}],"grants":[],"datasets":[],"versions":[],"referenced_works_count":14,"referenced_works":["https://openalex.org/W1019390808","https://openalex.org/W1509600527","https://openalex.org/W1582900148","https://openalex.org/W1597088765","https://openalex.org/W1998292918","https://openalex.org/W2005602803","https://openalex.org/W2014316444","https://openalex.org/W2055446421","https://openalex.org/W2108539060","https://openalex.org/W2120080222","https://openalex.org/W2168493238","https://openalex.org/W2552350602","https://openalex.org/W3145830094","https://openalex.org/W574591706"],"related_works":["https://openalex.org/W4385309418","https://openalex.org/W3207169898","https://openalex.org/W3204573923","https://openalex.org/W3198354237","https://openalex.org/W3011978806","https://openalex.org/W2743305891","https://openalex.org/W2604877941","https://openalex.org/W2535520145","https://openalex.org/W2331259470","https://openalex.org/W2019954703"],"abstract_inverted_index":{"Field":[0],"Programmable":[1],"Gate":[2],"Arrays":[3],"(FPGA)":[4],"are":[5],"often":[6],"the":[7,19,55,60,79,93],"go":[8],"to":[9,58,91],"choice":[10,116],"for":[11,44,63,77],"system":[12],"prototyping":[13],"and":[14,18,27,46,65,100,110],"comparison.":[15],"Circuit":[16],"design":[17],"impact":[20,94],"of":[21,85,95,117],"hardware":[22],"architecture":[23],"can":[24],"be":[25],"measured":[26],"experimented":[28],"with":[29,48,67],"using":[30],"short":[31],"iteration":[32],"times.":[33],"The":[34,102],"Verilog":[35],"To":[36],"Routing":[37],"(VTR)":[38],"CAD":[39],"flow":[40,62],"offers":[41],"a":[42,114],"framework":[43],"synthesis":[45],"experimentation":[47],"customizable":[49],"FPGA":[50,75],"architectures.":[51],"This":[52,71],"paper":[53],"describes":[54],"implemented":[56],"ability":[57],"use":[59],"VTR":[61],"tests":[64],"experiments":[66,86],"an":[68],"ARM":[69,80],"processor.":[70,81],"includes":[72],"different":[73],"possible":[74],"architectures":[76],"supporting":[78],"A":[82],"thorough":[83],"set":[84],"is":[87],"performed":[88],"which":[89],"aims":[90],"determine":[92],"hard":[96],"block":[97],"memories,":[98],"multipliers":[99,112],"adders.":[101],"results":[103],"suggest":[104],"that":[105],"2":[106],"bit":[107],"adder":[108],"units":[109],"36*36":[111],"offer":[113],"good":[115],"parameters.":[118]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W1990050178","counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2024-12-05T04:51:46.021384","created_date":"2016-06-24"}
