{"id":"https://openalex.org/W2113117663","doi":"https://doi.org/10.1109/mse.1997.612528","title":"Cache memory design for embedded systems based on program locality analysis","display_name":"Cache memory design for embedded systems based on program locality analysis","publication_year":2002,"publication_date":"2002-11-22","ids":{"openalex":"https://openalex.org/W2113117663","doi":"https://doi.org/10.1109/mse.1997.612528","mag":"2113117663"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/mse.1997.612528","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5012892451","display_name":"Roberto Giorgi","orcid":"https://orcid.org/0000-0003-0384-8229"},"institutions":[],"countries":["IT"],"is_corresponding":false,"raw_author_name":"R. Giorgi","raw_affiliation_strings":["Dipt. di Ingegneria della Inf, Pisa Univ., Italy"],"affiliations":[{"raw_affiliation_string":"Dipt. di Ingegneria della Inf, Pisa Univ., Italy","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076149166","display_name":"Cosimo Antonio Prete","orcid":"https://orcid.org/0000-0002-8467-8198"},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"C.A. Prete","raw_affiliation_strings":["Dipartimento di Ingegneria della Informazione, Universit\u00e0 di Pisa, Italy."],"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria della Informazione, Universit\u00e0 di Pisa, Italy.","institution_ids":["https://openalex.org/I108290504"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071445355","display_name":"G. Prina","orcid":null},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"G. Prina","raw_affiliation_strings":["Dipartimento di Ingegneria della Informazione, Universit\u00e0 di Pisa, Italy."],"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria della Informazione, Universit\u00e0 di Pisa, Italy.","institution_ids":["https://openalex.org/I108290504"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.559,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":5,"citation_normalized_percentile":{"value":0.61938,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":73,"max":75},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Performance Optimization","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Performance Optimization","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Reconfigurable Computing Systems and Design Methods","score":0.9995,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Networks on Chip in System-on-Chip Design","score":0.9994,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.6389873},{"id":"https://openalex.org/keywords/embedded-systems","display_name":"Embedded Systems","score":0.540357},{"id":"https://openalex.org/keywords/memory-systems","display_name":"Memory Systems","score":0.535042},{"id":"https://openalex.org/keywords/performance-optimization","display_name":"Performance Optimization","score":0.525683},{"id":"https://openalex.org/keywords/system-level-design","display_name":"System-Level Design","score":0.517137},{"id":"https://openalex.org/keywords/gpu-computing","display_name":"GPU Computing","score":0.510918},{"id":"https://openalex.org/keywords/locality-of-reference","display_name":"Locality of reference","score":0.4954735},{"id":"https://openalex.org/keywords/working-set","display_name":"Working set","score":0.46292496}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.85067},{"id":"https://openalex.org/C2779808786","wikidata":"https://www.wikidata.org/wiki/Q6664603","display_name":"Locality","level":2,"score":0.84949195},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6861183},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.6389873},{"id":"https://openalex.org/C31170391","wikidata":"https://www.wikidata.org/wiki/Q188619","display_name":"Hierarchy","level":2,"score":0.5299845},{"id":"https://openalex.org/C27602214","wikidata":"https://www.wikidata.org/wiki/Q1868547","display_name":"Locality of reference","level":3,"score":0.4954735},{"id":"https://openalex.org/C88196245","wikidata":"https://www.wikidata.org/wiki/Q8034984","display_name":"Working set","level":2,"score":0.46292496},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4575999},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3889598},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37731615},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.34491044},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.34372628},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1446352},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C34447519","wikidata":"https://www.wikidata.org/wiki/Q179522","display_name":"Market economy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/mse.1997.612528","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[],"grants":[],"datasets":[],"versions":[],"referenced_works_count":5,"referenced_works":["https://openalex.org/W1556885469","https://openalex.org/W2087802148","https://openalex.org/W2129552458","https://openalex.org/W2162107556","https://openalex.org/W374976041"],"related_works":["https://openalex.org/W2583128298","https://openalex.org/W2369223577","https://openalex.org/W2369125128","https://openalex.org/W2161159383","https://openalex.org/W2078036665","https://openalex.org/W2065777876","https://openalex.org/W2053359564","https://openalex.org/W1555349535","https://openalex.org/W1511204342","https://openalex.org/W1495260638"],"abstract_inverted_index":{"Cache":[0],"memory":[1,37,79],"design":[2],"in":[3,33],"embedded":[4,134],"systems":[5],"can":[6,30,66],"take":[7],"advantage":[8],"from":[9,97],"the":[10,13,23,36,51,57,60,70,94],"analysis":[11],"of":[12,35,53,100,128],"software":[14],"that":[15,18],"runs":[16],"on":[17,59],"system,":[19],"which":[20,46],"usually":[21],"remains":[22],"same":[24],"for":[25,77,133],"its":[26],"whole":[27],"life.":[28],"Programs":[29],"be":[31],"characterized,":[32],"respect":[34],"hierarchy,":[38],"using":[39],"locality":[40,52,102],"analysis.":[41],"We":[42],"propose":[43],"an":[44],"environment":[45,132],"permits":[47,90],"one":[48,91],"to":[49,92],"analyze":[50],"a":[54,116,129],"program":[55,95],"and":[56,75,80,107,122],"effects":[58],"target":[61],"system":[62,84],"performance.":[63],"The":[64,110],"student":[65],"thus":[67],"figure":[68],"out":[69],"best":[71],"tradeoff":[72],"between":[73],"costs":[74],"performance":[76,108],"cache":[78],"timings,":[81],"exploring":[82],"different":[83],"configurations.":[85],"A":[86],"fully":[87],"graphical":[88],"interface":[89],"observe":[93],"behavior":[96],"many":[98],"points":[99],"view:":[101],"surface,":[103],"working":[104],"set":[105],"evolution,":[106],"metrics.":[109],"tool":[111,118],"is":[112,124],"currently":[113],"used":[114],"as":[115,126],"teaching":[117],"at":[119],"our":[120],"University":[121],"it":[123],"distributed":[125],"part":[127],"commercial":[130],"development":[131],"systems.":[135]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2113117663","counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2024-11-27T13:51:41.293698","created_date":"2016-06-24"}
