{"id":"https://openalex.org/W4255381340","doi":"https://doi.org/10.1109/micro.1996.566446","title":"Integrating a misprediction recovery cache (MRC) into a superscalar pipeline","display_name":"Integrating a misprediction recovery cache (MRC) into a superscalar pipeline","publication_year":2002,"publication_date":"2002-12-24","ids":{"openalex":"https://openalex.org/W4255381340","doi":"https://doi.org/10.1109/micro.1996.566446"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/micro.1996.566446","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037714726","display_name":"J.O. Bondi","orcid":null},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J.O. Bondi","raw_affiliation_strings":["Semiconductor Group, Texas Instruments, Inc., Dallas, TX, USA"],"affiliations":[{"raw_affiliation_string":"Semiconductor Group, Texas Instruments, Inc., Dallas, TX, USA","institution_ids":["https://openalex.org/I74760111"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031668406","display_name":"A.K. Nanda","orcid":null},"institutions":[],"countries":["US"],"is_corresponding":false,"raw_author_name":"A.K. Nanda","raw_affiliation_strings":["T.J. Watson Research Center, IBM, Yorktown Heights, NY, USA"],"affiliations":[{"raw_affiliation_string":"T.J. Watson Research Center, IBM, Yorktown Heights, NY, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5085267545","display_name":"S. Dutta","orcid":null},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Dutta","raw_affiliation_strings":["Semiconductor Group, Texas Instruments, Inc., Dallas, TX, USA"],"affiliations":[{"raw_affiliation_string":"Semiconductor Group, Texas Instruments, Inc., Dallas, TX, USA","institution_ids":["https://openalex.org/I74760111"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.144,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":7,"citation_normalized_percentile":{"value":0.628864,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":76,"max":78},"biblio":{"volume":null,"issue":null,"first_page":"14","last_page":"23"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Performance Optimization","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Performance Optimization","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12326","display_name":"Algorithms and Architectures for Packet Classification","score":0.9963,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Distributed Storage Systems and Network Coding","score":0.996,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/superscalar","display_name":"Superscalar","score":0.6534425},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.6223226},{"id":"https://openalex.org/keywords/performance-optimization","display_name":"Performance Optimization","score":0.526753},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel Computing","score":0.511214},{"id":"https://openalex.org/keywords/branch-predictor","display_name":"Branch predictor","score":0.48666793}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8736239},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.77210855},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.72422945},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.6761997},{"id":"https://openalex.org/C175309249","wikidata":"https://www.wikidata.org/wiki/Q725864","display_name":"Pipeline transport","level":2,"score":0.66712373},{"id":"https://openalex.org/C147101560","wikidata":"https://www.wikidata.org/wiki/Q1045706","display_name":"Superscalar","level":2,"score":0.6534425},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.6223226},{"id":"https://openalex.org/C168522837","wikidata":"https://www.wikidata.org/wiki/Q679552","display_name":"Branch predictor","level":2,"score":0.48666793},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.46237063},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4104971},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.38682973},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.29916716},{"id":"https://openalex.org/C87717796","wikidata":"https://www.wikidata.org/wiki/Q146326","display_name":"Environmental engineering","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/micro.1996.566446","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[],"grants":[],"datasets":[],"versions":[],"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W4300808405","https://openalex.org/W4246045282","https://openalex.org/W2383295287","https://openalex.org/W2170860052","https://openalex.org/W2150776253","https://openalex.org/W2131679972","https://openalex.org/W2120025253","https://openalex.org/W2071915432","https://openalex.org/W1977470888","https://openalex.org/W117871465"],"abstract_inverted_index":{"In":[0,107],"modern":[1,47],"processors,":[2],"deep":[3],"pipelines":[4],"couple":[5],"with":[6],"superscalar":[7],"techniques":[8],"to":[9,14,72],"allow":[10],"each":[11],"pipe":[12,21],"stage":[13],"process":[15],"multiple":[16],"instructions.":[17],"When":[18],"such":[19],"a":[20,33,69],"must":[22],"be":[23,87],"pushed":[24],"and":[25],"refilled,":[26],"as":[27,38],"when":[28],"predicted":[29],"program":[30],"flow":[31],"beyond":[32],"branch":[34,48,66],"is":[35,44,68,104],"subsequently":[36],"recognized":[37],"wrong,":[39],"the":[40,59,64,99],"temporary":[41],"performance":[42],"loss":[43],"significant.":[45],"While":[46],"target":[49],"buffer":[50],"(BTB)":[51],"technology":[52],"makes":[53],"this":[54,82,108],"flush/refill":[55],"penalty":[56,60,85],"fairly":[57],"rare,":[58],"that":[61,79],"accrues":[62],"from":[63],"remaining":[65],"mispredictions":[67],"serious":[70],"impediment":[71],"even":[73],"higher":[74],"processor":[75],"performance.":[76],"Advanced":[77],"mechanisms":[78],"can":[80,86],"reduce":[81],"residual":[83],"misprediction":[84],"of":[88],"enormous":[89],"value":[90],"in":[91],"future":[92],"microprocessor":[93],"designs.":[94],"One":[95],"promising":[96],"new":[97],"mechanism,":[98],"Misprediction":[100],"Recovery":[101],"Cache":[102],"(MRC)":[103],"proposed":[105],"previously.":[106],"paper,":[109],"we":[110],"focus":[111],"especially":[112],"on":[113],"MRC":[114],"integration":[115],"into":[116],"existing":[117],"pipelines.":[118]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W4255381340","counts_by_year":[{"year":2024,"cited_by_count":1}],"updated_date":"2024-09-25T06:18:16.175087","created_date":"2022-05-12"}