{"id":"https://openalex.org/W2513880371","doi":"https://doi.org/10.1109/isvlsi.2016.131","title":"SoC, NoC and Hierarchical Bus Implementations of Applications on FPGAs Using the FCUDA Flow","display_name":"SoC, NoC and Hierarchical Bus Implementations of Applications on FPGAs Using the FCUDA Flow","publication_year":2016,"publication_date":"2016-07-01","ids":{"openalex":"https://openalex.org/W2513880371","doi":"https://doi.org/10.1109/isvlsi.2016.131","mag":"2513880371"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi.2016.131","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101399125","display_name":"Tan Nguyen","orcid":"https://orcid.org/0000-0003-3748-403X"},"institutions":[{"id":"https://openalex.org/I4210108443","display_name":"Advanced Digital Sciences Center","ror":"https://ror.org/01xaqx887","country_code":"SG","type":"facility","lineage":["https://openalex.org/I4210108443"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Tan Nguyen","raw_affiliation_strings":["Advanced Digital Sciences Center, Singapore"],"affiliations":[{"raw_affiliation_string":"Advanced Digital Sciences Center, Singapore","institution_ids":["https://openalex.org/I4210108443"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108106597","display_name":"Yao Cheny","orcid":null},"institutions":[{"id":"https://openalex.org/I205237279","display_name":"Nankai University","ror":"https://ror.org/01y1kjr75","country_code":"CN","type":"education","lineage":["https://openalex.org/I205237279"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yao Cheny","raw_affiliation_strings":["Nankai University, Tianjin, Tianjin, CN"],"affiliations":[{"raw_affiliation_string":"Nankai University, Tianjin, Tianjin, CN","institution_ids":["https://openalex.org/I205237279"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090843153","display_name":"Kyle Rupnow","orcid":"https://orcid.org/0000-0003-2908-2225"},"institutions":[{"id":"https://openalex.org/I4210108443","display_name":"Advanced Digital Sciences Center","ror":"https://ror.org/01xaqx887","country_code":"SG","type":"facility","lineage":["https://openalex.org/I4210108443"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Kyle Rupnow","raw_affiliation_strings":["Advanced Digital Sciences Center, Singapore"],"affiliations":[{"raw_affiliation_string":"Advanced Digital Sciences Center, Singapore","institution_ids":["https://openalex.org/I4210108443"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026163196","display_name":"Swathi Gurumani","orcid":null},"institutions":[{"id":"https://openalex.org/I4210108443","display_name":"Advanced Digital Sciences Center","ror":"https://ror.org/01xaqx887","country_code":"SG","type":"facility","lineage":["https://openalex.org/I4210108443"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Swathi Gurumani","raw_affiliation_strings":["Advanced Digital Sciences Center, Singapore"],"affiliations":[{"raw_affiliation_string":"Advanced Digital Sciences Center, Singapore","institution_ids":["https://openalex.org/I4210108443"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100394256","display_name":"Yao Chen","orcid":"https://orcid.org/0000-0002-5798-2282"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Deming Chen","raw_affiliation_strings":["University of Illinois at Urbana-Champaign"],"affiliations":[{"raw_affiliation_string":"University of Illinois at Urbana-Champaign","institution_ids":["https://openalex.org/I157725225"]}]}],"institution_assertions":[],"countries_distinct_count":3,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.271,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":2,"citation_normalized_percentile":{"value":0.437757,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":73,"max":77},"biblio":{"volume":null,"issue":null,"first_page":"661","last_page":"666"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Reconfigurable Computing Systems and Design Methods","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Reconfigurable Computing Systems and Design Methods","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Networks on Chip in System-on-Chip Design","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Performance Optimization","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.6196947},{"id":"https://openalex.org/keywords/simd","display_name":"SIMD","score":0.5755887},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.533063},{"id":"https://openalex.org/keywords/fpga","display_name":"FPGA","score":0.526577},{"id":"https://openalex.org/keywords/dataflow-programming-languages","display_name":"Dataflow Programming Languages","score":0.519189},{"id":"https://openalex.org/keywords/gpu-computing","display_name":"GPU Computing","score":0.508271},{"id":"https://openalex.org/keywords/multicore-architectures","display_name":"Multicore Architectures","score":0.507635},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.41342953}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8040252},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7346895},{"id":"https://openalex.org/C2778119891","wikidata":"https://www.wikidata.org/wiki/Q477690","display_name":"CUDA","level":2,"score":0.671793},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.63198495},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.6196947},{"id":"https://openalex.org/C150552126","wikidata":"https://www.wikidata.org/wiki/Q339387","display_name":"SIMD","level":2,"score":0.5755887},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.533063},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.49635106},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.41342953},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.36843944},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.1334013}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi.2016.131","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.64,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"grants":[],"datasets":[],"versions":[],"referenced_works_count":14,"referenced_works":["https://openalex.org/W1976366480","https://openalex.org/W2000921084","https://openalex.org/W2045856677","https://openalex.org/W2049600101","https://openalex.org/W2054625910","https://openalex.org/W2073137766","https://openalex.org/W2075160498","https://openalex.org/W2080592089","https://openalex.org/W2081228314","https://openalex.org/W2108019747","https://openalex.org/W2141597697","https://openalex.org/W2294577437","https://openalex.org/W2342489538","https://openalex.org/W4252796023"],"related_works":["https://openalex.org/W4313484792","https://openalex.org/W4312985392","https://openalex.org/W4283730710","https://openalex.org/W4281926497","https://openalex.org/W4281784598","https://openalex.org/W4250699891","https://openalex.org/W2921149022","https://openalex.org/W2269990635","https://openalex.org/W2160542743","https://openalex.org/W2042762783"],"abstract_inverted_index":{"The":[0,26,53],"FCUDA":[1,54],"project":[2,55],"aims":[3],"to":[4,46,50,62,98],"improve":[5],"programmability":[6],"of":[7,11,22],"FPGAs":[8],"and":[9,78,95],"expression":[10],"application":[12,107],"parallelism":[13],"in":[14],"High":[15],"Level":[16],"Synthesis":[17],"(HLS)":[18],"through":[19],"the":[20,23,59,68,109],"use":[21],"CUDA":[24,27,61],"language.":[25],"language":[28,38],"is":[29],"a":[30],"popular":[31],"single-instruction":[32],"multiple":[33],"data":[34],"(SIMD)":[35],"style":[36],"programming":[37],"with":[39,81],"wide":[40],"adoption,":[41],"thus":[42],"offering":[43],"significant":[44],"opportunity":[45],"bring":[47],"experienced":[48],"programmers":[49],"FPGA":[51],"computing.":[52],"now":[56],"has":[57],"open-sourced":[58],"core":[60],"RTL":[63],"transformation":[64],"as":[65,67],"well":[66],"infrastructure":[69,104],"for":[70,101,105,108],"design":[71,91],"space":[72,92],"exploration,":[73,93],"bus-based":[74],"andNoC-based":[75],"on-chip":[76],"communications,":[77],"platform":[79,96],"integration":[80,97],"Xilinx's":[82],"SoC":[83],"systems.":[84],"In":[85],"this":[86],"paper,":[87],"we":[88],"present":[89,99],"FCUDA's":[90],"interconnect":[94],"guidelines":[100],"selecting":[102],"system-level":[103],"an":[106],"best":[110],"implementation.":[111]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2513880371","counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2024-10-14T11:11:51.596691","created_date":"2016-09-16"}