iBet uBet web content aggregator. Adding the entire web to your favor.
iBet uBet web content aggregator. Adding the entire web to your favor.



Link to original content: https://api.openalex.org/works/doi:10.1109/ICECS.1996.582696
{"id":"https://openalex.org/W2112095471","doi":"https://doi.org/10.1109/icecs.1996.582696","title":"Accurate timing model for the CMOS inverter","display_name":"Accurate timing model for the CMOS inverter","publication_year":2002,"publication_date":"2002-12-24","ids":{"openalex":"https://openalex.org/W2112095471","doi":"https://doi.org/10.1109/icecs.1996.582696","mag":"2112095471"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.1996.582696","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088545509","display_name":"L. Bisdounis","orcid":null},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"L. Bisdounis","raw_affiliation_strings":["VLSI Design Laboratory Department of Electrical & Computer Engineering, University of Patras, Patras, Greece"],"affiliations":[{"raw_affiliation_string":"VLSI Design Laboratory Department of Electrical & Computer Engineering, University of Patras, Patras, Greece","institution_ids":["https://openalex.org/I174878644"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023894427","display_name":"S. Nikolaidis","orcid":"https://orcid.org/0000-0002-9794-8062"},"institutions":[{"id":"https://openalex.org/I21370196","display_name":"Aristotle University of Thessaloniki","ror":"https://ror.org/02j61yw88","country_code":"GR","type":"education","lineage":["https://openalex.org/I21370196"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"S. Nikolaidis","raw_affiliation_strings":["Electronics & Computers Division, Department of Physics, University of Thessaloniki, Thessaloniki, Greece"],"affiliations":[{"raw_affiliation_string":"Electronics & Computers Division, Department of Physics, University of Thessaloniki, Thessaloniki, Greece","institution_ids":["https://openalex.org/I21370196"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090802119","display_name":"Odysseas Koufopavlou","orcid":null},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"O. Koufopavlou","raw_affiliation_strings":["VLSI Design Laboratory Department of Electrical & Computer Engineering, University of Patras, Patras, Greece"],"affiliations":[{"raw_affiliation_string":"VLSI Design Laboratory Department of Electrical & Computer Engineering, University of Patras, Patras, Greece","institution_ids":["https://openalex.org/I174878644"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112615786","display_name":"C.E. Goutis","orcid":null},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"C. Goutis","raw_affiliation_strings":["VLSI Design Laboratory Department of Electrical & Computer Engineering, University of Patras, Patras, Greece"],"affiliations":[{"raw_affiliation_string":"VLSI Design Laboratory Department of Electrical & Computer Engineering, University of Patras, Patras, Greece","institution_ids":["https://openalex.org/I174878644"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":0,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":0,"max":57},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9995,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9993,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/semiconductor-device-modeling","display_name":"Semiconductor device modeling","score":0.41201532}],"concepts":[{"id":"https://openalex.org/C197424946","wikidata":"https://www.wikidata.org/wiki/Q1165717","display_name":"Waveform","level":3,"score":0.9090835},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.8642205},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.72678494},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.68620104},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6090585},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.51346356},{"id":"https://openalex.org/C131584629","wikidata":"https://www.wikidata.org/wiki/Q4308705","display_name":"Coupling (piping)","level":2,"score":0.44497928},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4332999},{"id":"https://openalex.org/C4775677","wikidata":"https://www.wikidata.org/wiki/Q7449393","display_name":"Semiconductor device modeling","level":3,"score":0.41201532},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.40866736},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.27055684},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.22136104},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.19515452},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.1996.582696","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.73,"display_name":"Affordable and clean energy"}],"grants":[],"datasets":[],"versions":[],"referenced_works_count":7,"referenced_works":["https://openalex.org/W1565760642","https://openalex.org/W2011576211","https://openalex.org/W2022892565","https://openalex.org/W2055510065","https://openalex.org/W2087237681","https://openalex.org/W2134067926","https://openalex.org/W2577016145"],"related_works":["https://openalex.org/W4367555392","https://openalex.org/W3040712279","https://openalex.org/W2891188466","https://openalex.org/W2374664672","https://openalex.org/W2364769705","https://openalex.org/W2226796451","https://openalex.org/W2176409448","https://openalex.org/W2129841057","https://openalex.org/W2056136368","https://openalex.org/W1974895211"],"abstract_inverted_index":{"This":[0],"paper":[1],"introduces":[2],"an":[3],"accurate,":[4],"analytical":[5],"timing":[6],"model":[7],"for":[8,16],"the":[9,18,32,36,40],"CMOS":[10],"inverter.":[11],"Analytical":[12],"output":[13],"waveform":[14,24],"expressions":[15],"all":[17],"inverter":[19],"operation":[20],"regions":[21],"and":[22,39],"input":[23],"slopes":[25],"are":[26],"derived,":[27],"which":[28],"take":[29],"into":[30],"account":[31],"complete":[33],"expression":[34],"of":[35],"short-circuit":[37],"current":[38],"gate-to-drain":[41],"coupling":[42],"capacitance.":[43]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2112095471","counts_by_year":[],"updated_date":"2024-12-10T16:22:58.900243","created_date":"2016-06-24"}