iBet uBet web content aggregator. Adding the entire web to your favor.
iBet uBet web content aggregator. Adding the entire web to your favor.



Link to original content: https://api.openalex.org/works/doi:10.1109/HPCSIM.2013.6641395
{"id":"https://openalex.org/W2130928156","doi":"https://doi.org/10.1109/hpcsim.2013.6641395","title":"Autonomic scheduling of tasks from data parallel patterns to CPU/GPU core mixes","display_name":"Autonomic scheduling of tasks from data parallel patterns to CPU/GPU core mixes","publication_year":2013,"publication_date":"2013-07-01","ids":{"openalex":"https://openalex.org/W2130928156","doi":"https://doi.org/10.1109/hpcsim.2013.6641395","mag":"2130928156"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpcsim.2013.6641395","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5081450414","display_name":"T. Serban","orcid":null},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"T. Serban","raw_affiliation_strings":["Dept. Computer Science, University of Pisa, PISA, Italy"],"affiliations":[{"raw_affiliation_string":"Dept. Computer Science, University of Pisa, PISA, Italy","institution_ids":["https://openalex.org/I108290504"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051951613","display_name":"Marco Danelutto","orcid":"https://orcid.org/0000-0002-7433-376X"},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Danelutto","raw_affiliation_strings":["Dept. Computer Science, University of Pisa, PISA, Italy"],"affiliations":[{"raw_affiliation_string":"Dept. Computer Science, University of Pisa, PISA, Italy","institution_ids":["https://openalex.org/I108290504"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5014362102","display_name":"Peter Kilpatrick","orcid":"https://orcid.org/0000-0003-0818-8979"},"institutions":[{"id":"https://openalex.org/I126231945","display_name":"Queen's University Belfast","ror":"https://ror.org/00hswnk62","country_code":"GB","type":"education","lineage":["https://openalex.org/I126231945"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"P. Kilpatrick","raw_affiliation_strings":["Dept. Comput. Sci., Queen's Univ. of Belfast - UK, Belfast, UK"],"affiliations":[{"raw_affiliation_string":"Dept. Comput. Sci., Queen's Univ. of Belfast - UK, Belfast, UK","institution_ids":["https://openalex.org/I126231945"]}]}],"institution_assertions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.788,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":7,"citation_normalized_percentile":{"value":0.546021,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":83,"max":84},"biblio":{"volume":null,"issue":null,"first_page":"72","last_page":"79"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Performance Optimization","score":0.9998,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Performance Optimization","score":0.9998,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed Grid Computing Systems","score":0.9996,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Reconfigurable Computing Systems and Design Methods","score":0.9974,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/task-scheduling","display_name":"Task Scheduling","score":0.623023},{"id":"https://openalex.org/keywords/gpu-computing","display_name":"GPU Computing","score":0.61254},{"id":"https://openalex.org/keywords/performance-optimization","display_name":"Performance Optimization","score":0.609143},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel Computing","score":0.597238},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5689707},{"id":"https://openalex.org/keywords/heterogeneous-computing","display_name":"Heterogeneous Computing","score":0.55756},{"id":"https://openalex.org/keywords/processor-scheduling","display_name":"Processor scheduling","score":0.4692027},{"id":"https://openalex.org/keywords/many-core","display_name":"Many core","score":0.41113883}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8714187},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.69374555},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5689707},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.54031706},{"id":"https://openalex.org/C2984822820","wikidata":"https://www.wikidata.org/wiki/Q1123036","display_name":"Processor scheduling","level":3,"score":0.4692027},{"id":"https://openalex.org/C3020431745","wikidata":"https://www.wikidata.org/wiki/Q25325220","display_name":"Many core","level":2,"score":0.41113883},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2557915},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.04926294},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpcsim.2013.6641395","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[],"grants":[],"datasets":[],"versions":[],"referenced_works_count":13,"referenced_works":["https://openalex.org/W1578415644","https://openalex.org/W164384110","https://openalex.org/W2032401773","https://openalex.org/W2039417226","https://openalex.org/W2096448787","https://openalex.org/W2104861744","https://openalex.org/W2147139699","https://openalex.org/W2150952308","https://openalex.org/W2151788546","https://openalex.org/W2256063247","https://openalex.org/W4206836497","https://openalex.org/W4237609491","https://openalex.org/W50182133"],"related_works":["https://openalex.org/W4248099758","https://openalex.org/W2979015021","https://openalex.org/W2918840249","https://openalex.org/W2807819249","https://openalex.org/W2110053126","https://openalex.org/W2104702637","https://openalex.org/W2079303253","https://openalex.org/W2023938924","https://openalex.org/W1993191611","https://openalex.org/W1991859582"],"abstract_inverted_index":{"We":[0],"propose":[1],"a":[2,75,97,105,166],"methodology":[3,23],"for":[4,35],"optimizing":[5],"the":[6,18,45,50,64,70,85,111,134,176,179],"execution":[7,47,191],"of":[8,17,49,100,136,150,175],"data":[9,52,71,116,170],"parallel":[10,53,72,117,171],"(sub-)tasks":[11],"on":[12,26,141,195],"CPU":[13,39,88,107,142,184],"and":[14,40,57,89,108,128,143,154,181,207],"GPU":[15,41,90,109,144,180],"cores":[16,145,151,185],"same":[19],"heterogeneous":[20],"architecture.":[21],"The":[22,92,120,159],"is":[24,55],"based":[25],"two":[27],"main":[28],"components:":[29],"i)":[30],"an":[31,59],"analytical":[32,65,93],"performance":[33,66,94,155,204],"model":[34,67,95,121,205],"scheduling":[36,173],"tasks":[37,112,137,177],"among":[38],"cores,":[42],"such":[43,146],"that":[44,147,201],"global":[46],"time":[48],"overall":[51],"pattern":[54,172],"optimized;":[56],"ii)":[58],"autonomic":[60,77,160,208],"module":[61,209],"which":[62],"uses":[63,96],"to":[68,83,103,138,178,183,188],"implement":[69],"computations":[73],"in":[74,163],"completely":[76],"way,":[78],"requiring":[79],"no":[80],"programmer":[81],"intervention":[82],"optimize":[84],"computation":[86],"across":[87],"cores.":[91],"small":[98],"set":[99],"simple":[101],"parameters":[102],"devise":[104],"partitioning-between":[106],"cores-of":[110],"derived":[113],"from":[114],"structured":[115],"patterns/algorithmic":[118],"skeletons.":[119],"takes":[122],"into":[123],"account":[124],"both":[125,148,203],"hardware":[126],"related":[127],"application":[129],"dependent":[130],"parameters.":[131],"It":[132],"computes":[133],"percentage":[135],"be":[139],"executed":[140],"kinds":[149],"are":[152,157,199],"exploited":[153],"figures":[156],"optimized.":[158],"module,":[161],"implemented":[162],"FastFlow,":[164],"executes":[165],"generic":[167],"map":[168],"(reduce)":[169],"part":[174,182],"so":[186],"as":[187],"achieve":[189],"optimal":[190],"time.":[192],"Experimental":[193],"results":[194],"state-of-the-art":[196],"CPU/GPU":[197],"architectures":[198],"shown":[200],"assess":[202],"properties":[206],"effectiveness.":[210]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2130928156","counts_by_year":[{"year":2020,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2}],"updated_date":"2024-11-26T09:24:00.061227","created_date":"2016-06-24"}