{"id":"https://openalex.org/W4385250304","doi":"https://doi.org/10.1109/eit57321.2023.10187218","title":"Hardware Description of Event-driven Systems by Translation of UML Statecharts to VHDL","display_name":"Hardware Description of Event-driven Systems by Translation of UML Statecharts to VHDL","publication_year":2023,"publication_date":"2023-05-18","ids":{"openalex":"https://openalex.org/W4385250304","doi":"https://doi.org/10.1109/eit57321.2023.10187218"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/eit57321.2023.10187218","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5086561910","display_name":"Cristinel Ababei","orcid":"https://orcid.org/0000-0002-7609-5304"},"institutions":[{"id":"https://openalex.org/I102461120","display_name":"Marquette University","ror":"https://ror.org/04gr4te78","country_code":"US","type":"education","lineage":["https://openalex.org/I102461120"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Cristinel Ababei","raw_affiliation_strings":["Electrical and Computer Engineering Dept., Marquette University, Milwaukee, WI, USA"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Dept., Marquette University, Milwaukee, WI, USA","institution_ids":["https://openalex.org/I102461120"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5062429674","display_name":"Susan C. Schneider","orcid":"https://orcid.org/0000-0002-8971-897X"},"institutions":[{"id":"https://openalex.org/I102461120","display_name":"Marquette University","ror":"https://ror.org/04gr4te78","country_code":"US","type":"education","lineage":["https://openalex.org/I102461120"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Susan C. Schneider","raw_affiliation_strings":["Electrical and Computer Engineering Dept., Marquette University, Milwaukee, WI, USA"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Dept., Marquette University, Milwaukee, WI, USA","institution_ids":["https://openalex.org/I102461120"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":0,"max":68},"biblio":{"volume":null,"issue":null,"first_page":"071","last_page":"076"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9989,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9989,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.9981,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.61353034}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8324332},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.8139914},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.622369},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.61353034},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.5902624},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.5863954},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.58429456},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5302315},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.5298476},{"id":"https://openalex.org/C145644426","wikidata":"https://www.wikidata.org/wiki/Q169411","display_name":"Unified Modeling Language","level":3,"score":0.491705},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.4770305},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.41413206},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.19943044},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.16497496},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/eit57321.2023.10187218","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[],"grants":[],"datasets":[],"versions":[],"referenced_works_count":12,"referenced_works":["https://openalex.org/W1533978867","https://openalex.org/W1534770471","https://openalex.org/W1985018588","https://openalex.org/W2035127551","https://openalex.org/W206452102","https://openalex.org/W2099529102","https://openalex.org/W2110018574","https://openalex.org/W2999162532","https://openalex.org/W3041945359","https://openalex.org/W40309502","https://openalex.org/W4236468831","https://openalex.org/W568055057"],"related_works":["https://openalex.org/W2537479781","https://openalex.org/W2391435730","https://openalex.org/W2384838054","https://openalex.org/W2381282135","https://openalex.org/W2366672283","https://openalex.org/W2139058049","https://openalex.org/W2111408175","https://openalex.org/W2110818533","https://openalex.org/W1917852300","https://openalex.org/W146887057"],"abstract_inverted_index":{"We":[0,192],"present":[1],"a":[2,16,37,46,62,91,118,199,221],"complete":[3],"implementation":[4,207],"prototype":[5,200],"of":[6,59,117,120,136,145,175,201],"the":[7,24,57,109,137,143,151,159,164,169,176,194,202,214],"classic":[8,203],"Fly-n-Shoot":[9,204],"game":[10,18],"on":[11,61,211],"an":[12,30],"FPGA.":[13],"This":[14,114,162],"is":[15,179,208],"famous":[17],"that":[19,219],"has":[20,36],"been":[21],"described":[22],"in":[23,86],"past":[25],"using":[26,45,108],"UML":[27,96,160],"statecharts":[28,97,124],"as":[29,52],"event-driven":[31,101],"embedded":[32,102],"system.":[33],"Because":[34],"it":[35,44,178],"rather":[38],"complex":[39],"functionality,":[40],"attempting":[41],"to":[42,71,77,81,99,142,149,158,197],"describe":[43,90,150],"hardware":[47],"description":[48],"language":[49],"(HDL),":[50],"such":[51],"VHDL":[53,105,127,147],"or":[54,182],"Verilog,":[55],"with":[56],"goal":[58],"deploying":[60],"real":[63,212],"FPGA":[64,216,224],"becomes":[65],"challenging.":[66],"As":[67],"such,":[68],"brute-force":[69],"attempts":[70],"write":[72],"HDL":[73],"descriptions":[74],"are":[75,140],"prone":[76],"errors":[78],"and":[79,131,171,185,188],"subject":[80],"long":[82],"design":[83,134],"times.":[84],"Hence,":[85],"this":[87],"paper,":[88],"we":[89],"practical":[92],"approach":[93,115,139,196],"for":[94],"translating":[95],"used":[98],"specify":[100],"systems":[103],"into":[104,126],"code":[106],"written":[107],"popular":[110],"two-process":[111,146],"coding":[112,148],"style.":[113],"consists":[116],"set":[119],"mapping":[121],"rules":[122],"from":[123],"concepts":[125],"constructs.":[128],"The":[129,206],"efficacy":[130],"correct":[132],"by":[133],"characteristics":[135],"presented":[138],"due":[141],"use":[144],"hierarchical":[152],"finite":[153],"state":[154,173],"machine":[155],"(FSM)":[156],"corresponding":[157],"statecharts.":[161],"gives":[163],"designer":[165],"better":[166],"control":[167],"over":[168],"current":[170],"next":[172],"signals":[174],"FSMs,":[177],"more":[180],"modular":[181],"object":[183],"oriented,":[184],"makes":[186],"development":[187,217],"debugging":[189],"much":[190],"easier.":[191],"apply":[193],"proposed":[195],"implement":[198],"game.":[205],"verified":[209],"successfully":[210],"hardware,":[213],"DE1-SoC":[215],"board,":[218],"uses":[220],"Cyclone":[222],"IV":[223],"chip.":[225]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W4385250304","counts_by_year":[],"updated_date":"2024-12-10T22:48:48.781230","created_date":"2023-07-26"}
