iBet uBet web content aggregator. Adding the entire web to your favor.
iBet uBet web content aggregator. Adding the entire web to your favor.



Link to original content: https://api.openalex.org/works/doi:10.1109/DSD.2013.67
{"id":"https://openalex.org/W2071667756","doi":"https://doi.org/10.1109/dsd.2013.67","title":"A Distributed BIST Scheme for NoC-Based Memory Cores","display_name":"A Distributed BIST Scheme for NoC-Based Memory Cores","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W2071667756","doi":"https://doi.org/10.1109/dsd.2013.67","mag":"2071667756"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2013.67","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053246915","display_name":"Bibhas Ghoshal","orcid":"https://orcid.org/0000-0002-8228-6481"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Bibhas Ghoshal","raw_affiliation_strings":["Dept. of Computer Science and Engg, Indian Institute of Technology Kharagpur, Kharagpur, India"],"affiliations":[{"raw_affiliation_string":"Dept. of Computer Science and Engg, Indian Institute of Technology Kharagpur, Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103023953","display_name":"Indranil Sengupta","orcid":"https://orcid.org/0000-0002-5438-6653"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Indranil Sengupta","raw_affiliation_strings":["Dept. of Computer Science and Engg, Indian Institute of Technology Kharagpur, Kharagpur, India"],"affiliations":[{"raw_affiliation_string":"Dept. of Computer Science and Engg, Indian Institute of Technology Kharagpur, Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":3,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":76,"max":78},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"Very Large Scale Integration Testing","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"Very Large Scale Integration Testing","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Networks on Chip in System-on-Chip Design","score":0.9997,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Fault Tolerance in Electronic Systems","score":0.9974,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.75972366},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.61800265},{"id":"https://openalex.org/keywords/bist-scheme","display_name":"BIST Scheme","score":0.603347},{"id":"https://openalex.org/keywords/test-access-architecture","display_name":"Test Access Architecture","score":0.55124},{"id":"https://openalex.org/keywords/noc-architecture","display_name":"NoC Architecture","score":0.538853},{"id":"https://openalex.org/keywords/system-on-a-chip-test","display_name":"System-on-a-Chip Test","score":0.530723},{"id":"https://openalex.org/keywords/embedded-cores","display_name":"Embedded Cores","score":0.517881},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.43170422}],"concepts":[{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.75972366},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.67931163},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.67060995},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6457249},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.61800265},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.60849816},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4734782},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.4660175},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4528464},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.43170422},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42656094},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33680466},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11871734},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2013.67","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.43,"display_name":"Industry, innovation and infrastructure"}],"grants":[],"datasets":[],"versions":[],"referenced_works_count":17,"referenced_works":["https://openalex.org/W132998242","https://openalex.org/W1548168045","https://openalex.org/W1572969092","https://openalex.org/W1972090007","https://openalex.org/W2005756324","https://openalex.org/W2042830732","https://openalex.org/W2087332139","https://openalex.org/W2102494215","https://openalex.org/W2104293897","https://openalex.org/W2112502828","https://openalex.org/W2114185924","https://openalex.org/W2120392299","https://openalex.org/W2128510599","https://openalex.org/W2144546432","https://openalex.org/W2151243068","https://openalex.org/W3145297239","https://openalex.org/W4234792749"],"related_works":["https://openalex.org/W3175523456","https://openalex.org/W3037187668","https://openalex.org/W2904405156","https://openalex.org/W2160704485","https://openalex.org/W2154560316","https://openalex.org/W2112804590","https://openalex.org/W2105031241","https://openalex.org/W2077105843","https://openalex.org/W2032837518","https://openalex.org/W2001585562"],"abstract_inverted_index":{"This":[0],"paper":[1,69],"proposes":[2,71],"a":[3,12,44,58,66,72,101],"distributed":[4,122],"Memory":[5],"Built-":[6],"In-Self":[7],"Test":[8],"(MBIST)":[9],"architecture":[10,78,124],"employing":[11],"hybrid":[13],"technique":[14],"for":[15,75,119],"testing":[16],"heterogeneous":[17],"memory":[18,28],"cores":[19,29,56],"interconnected":[20],"using":[21],"NoC.":[22],"In":[23],"the":[24,27,55,61,76,81,85,120],"proposed":[25,77,97,121],"architecture,":[26],"are":[30,63],"placed":[31],"in":[32,57,65,125],"different":[33],"groups":[34,62],"based":[35],"on":[36,53,90],"distance":[37],"and":[38],"timing":[39],"constraints.":[40],"Each":[41],"group":[42,59],"has":[43],"dedicated":[45,109],"BIST":[46,110,123],"controller":[47],"which":[48],"performs":[49,100],"parallel":[50],"March":[51],"test":[52,73,82,98,105],"all":[54],"while":[60],"tested":[64],"pipeline.":[67],"The":[68],"also":[70],"schedule":[74,99],"to":[79,108,127],"keep":[80],"power":[83,86,103],"within":[84],"budget.":[87],"Experiments":[88],"performed":[89],"ITC'02":[91],"benchmark":[92],"circuit":[93],"confirms":[94],"that":[95],"our":[96],"more":[102],"constrained":[104],"as":[106],"compared":[107],"technique.":[111],"Moreover,":[112],"experimental":[113],"results":[114],"indicate":[115],"real":[116],"estate":[117],"benefits":[118],"comparison":[126],"other":[128],"reported":[129],"techniques.":[130]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2071667756","counts_by_year":[{"year":2024,"cited_by_count":3}],"updated_date":"2024-09-26T22:31:46.803462","created_date":"2016-06-24"}