{"id":"https://openalex.org/W2013815172","doi":"https://doi.org/10.1109/43.489105","title":"Retiming revisited and reversed","display_name":"Retiming revisited and reversed","publication_year":1996,"publication_date":"1996-03-01","ids":{"openalex":"https://openalex.org/W2013815172","doi":"https://doi.org/10.1109/43.489105","mag":"2013815172"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/43.489105","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"journal-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064059676","display_name":"Guy Even","orcid":"https://orcid.org/0000-0001-5407-330X"},"institutions":[{"id":"https://openalex.org/I91712215","display_name":"Saarland University","ror":"https://ror.org/01jdpyv68","country_code":"DE","type":"education","lineage":["https://openalex.org/I91712215"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"G. Even","raw_affiliation_strings":["Saarlandes Univ., Saarbrucken, Germany"],"affiliations":[{"raw_affiliation_string":"Saarlandes Univ., Saarbrucken, Germany","institution_ids":["https://openalex.org/I91712215"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019864669","display_name":"I. Spillinger","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"I.Y. Spillinger","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5082318082","display_name":"Leon Stok","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"L. Stok","raw_affiliation_strings":["[IBM Thomas J. Watson Research Center, Yorktown Heights, NY , USA]"],"affiliations":[{"raw_affiliation_string":"[IBM Thomas J. Watson Research Center, Yorktown Heights, NY , USA]","institution_ids":["https://openalex.org/I1341412227"]}]}],"institution_assertions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":8.366,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":65,"citation_normalized_percentile":{"value":0.94775,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":95},"biblio":{"volume":"15","issue":"3","first_page":"348","last_page":"357"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"Very Large Scale Integration Testing","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"Very Large Scale Integration Testing","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-Power VLSI Circuit Design and Optimization","score":0.9997,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"Design and Optimization of Field-Programmable Gate Arrays and Application-Specific Integrated Circuits","score":0.9988,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/retiming","display_name":"Retiming","score":0.99451554},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5606873},{"id":"https://openalex.org/keywords/statistical-timing-analysis","display_name":"Statistical Timing Analysis","score":0.517804},{"id":"https://openalex.org/keywords/power-optimization","display_name":"Power Optimization","score":0.513914},{"id":"https://openalex.org/keywords/kernel","display_name":"Kernel (algebra)","score":0.51093453}],"concepts":[{"id":"https://openalex.org/C41112130","wikidata":"https://www.wikidata.org/wiki/Q2146175","display_name":"Retiming","level":2,"score":0.99451554},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6593615},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5606873},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.55992275},{"id":"https://openalex.org/C74193536","wikidata":"https://www.wikidata.org/wiki/Q574844","display_name":"Kernel (algebra)","level":2,"score":0.51093453},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.44931948},{"id":"https://openalex.org/C2780586882","wikidata":"https://www.wikidata.org/wiki/Q7520643","display_name":"Simple (philosophy)","level":2,"score":0.4424737},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.438684},{"id":"https://openalex.org/C204241405","wikidata":"https://www.wikidata.org/wiki/Q461499","display_name":"Transformation (genetics)","level":3,"score":0.4241597},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.24480054},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.16793919},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12025264},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/43.489105","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[],"grants":[],"datasets":[],"versions":[],"referenced_works_count":12,"referenced_works":["https://openalex.org/W2087656024","https://openalex.org/W2099120582","https://openalex.org/W2120490412","https://openalex.org/W2125651818","https://openalex.org/W2135517247","https://openalex.org/W2148631003","https://openalex.org/W2150920965","https://openalex.org/W2151376499","https://openalex.org/W2152406824","https://openalex.org/W2172044541","https://openalex.org/W3143422391","https://openalex.org/W4250455229"],"related_works":["https://openalex.org/W2541396689","https://openalex.org/W2247596074","https://openalex.org/W2169017341","https://openalex.org/W2125110862","https://openalex.org/W2111485030","https://openalex.org/W2109887074","https://openalex.org/W2062977096","https://openalex.org/W2062802485","https://openalex.org/W2048768419","https://openalex.org/W1929354501"],"abstract_inverted_index":{"Retiming":[0],"is":[1,45,108],"a":[2,63,112],"very":[3],"promising":[4,18],"transformation":[5],"of":[6,22,41,48,66,70,111],"circuits":[7,23],"which":[8,117],"preserves":[9],"functionality":[10],"and":[11,38,72,87],"improves":[12],"performance.":[13],"Its":[14],"benefits":[15],"are":[16],"especially":[17],"in":[19,34,98],"automatic":[20],"synthesis":[21],"from":[24],"higher-level":[25],"descriptions.":[26],"However,":[27],"retiming":[28,68,115],"has":[29],"not":[30],"been":[31],"widely":[32],"included":[33],"current":[35],"design":[36],"tools":[37],"methodologies.":[39],"One":[40],"the":[42,46,55,67,79,89,92,109,124,137],"main":[43],"obstacles":[44],"problem":[47],"finding":[49],"an":[50,102,132],"equivalent":[51,84,103],"initial":[52,85,104,125,138],"state":[53,126,139],"for":[54,119],"retimed":[56],"circuit.":[57],"In":[58],"this":[59],"paper,":[60],"we":[61],"introduce":[62],"simple":[64],"modification":[65],"algorithm":[69,76,107],"Leiserson":[71],"Saxe.":[73],"The":[74,128],"modified":[75,97],"helps":[77],"minimize":[78],"effort":[80],"required":[81],"to":[82,95,100,135],"find":[83,101],"states":[86],"reduces":[88],"chance":[90],"that":[91],"network":[93],"needs":[94],"be":[96],"order":[99],"state.":[105],"This":[106],"kernel":[110],"new":[113],"efficient":[114],"method,":[116],"searches":[118],"optimal":[120],"retimings":[121],"while":[122],"preserving":[123],"condition.":[127],"paper":[129],"also":[130],"presents":[131],"improved":[133],"method":[134],"perform":[136],"calculation.":[140]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2013815172","counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2024-10-08T10:24:45.748854","created_date":"2016-06-24"}