{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,19]],"date-time":"2024-09-19T16:05:57Z","timestamp":1726761957260},"reference-count":132,"publisher":"MDPI AG","issue":"4","license":[{"start":{"date-parts":[[2020,4,6]],"date-time":"2020-04-06T00:00:00Z","timestamp":1586131200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Future Internet"],"abstract":"Modern datacenters are reinforcing the computational power and energy efficiency by assimilating field programmable gate arrays (FPGAs). The sustainability of this large-scale integration depends on enabling multi-tenant FPGAs. This requisite amplifies the importance of communication architecture and virtualization method with the required features in order to meet the high-end objective. Consequently, in the last decade, academia and industry proposed several virtualization techniques and hardware architectures for addressing resource management, scheduling, adoptability, segregation, scalability, performance-overhead, availability, programmability, time-to-market, security, and mainly, multitenancy. This paper provides an extensive survey covering three important aspects\u2014discussion on non-standard terms used in existing literature, network-on-chip evaluation choices as a mean to explore the communication architecture, and virtualization methods under latest classification. The purpose is to emphasize the importance of choosing appropriate communication architecture, virtualization technique and standard language to evolve the multi-tenant FPGAs in datacenters. None of the previous surveys encapsulated these aspects in one writing. Open problems are indicated for scientific community as well.<\/jats:p>","DOI":"10.3390\/fi12040064","type":"journal-article","created":{"date-parts":[[2020,4,7]],"date-time":"2020-04-07T07:58:39Z","timestamp":1586246319000},"page":"64","source":"Crossref","is-referenced-by-count":12,"title":["Revisiting the High-Performance Reconfigurable Computing for Future Datacenters"],"prefix":"10.3390","volume":"12","author":[{"ORCID":"http:\/\/orcid.org\/0000-0002-7448-4648","authenticated-orcid":false,"given":"Qaiser","family":"Ijaz","sequence":"first","affiliation":[{"name":"ImViA Laboratory, University of Burgundy, 21000 Dijon, France"},{"name":"Department of Computer System Engineering, Islamia University of Bahawalpur, Bahawalpur 63100, Pakistan"}]},{"given":"El-Bay","family":"Bourennane","sequence":"additional","affiliation":[{"name":"ImViA Laboratory, University of Burgundy, 21000 Dijon, France"}]},{"ORCID":"http:\/\/orcid.org\/0000-0003-2601-9327","authenticated-orcid":false,"given":"Ali Kashif","family":"Bashir","sequence":"additional","affiliation":[{"name":"Department of Computing and Mathematics, Manchester Metropolitan University, Manchester M15 6BH, UK"}]},{"given":"Hira","family":"Asghar","sequence":"additional","affiliation":[{"name":"Department of Computer System Engineering, Islamia University of Bahawalpur, Bahawalpur 63100, Pakistan"}]}],"member":"1968","published-online":{"date-parts":[[2020,4,6]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"600","DOI":"10.1109\/TPDS.2015.2407896","article-title":"Suitability analysis of FPGAs for heterogeneous platforms in HPC","volume":"27","author":"Escobar","year":"2016","journal-title":"IEEE Trans. Parallel Distrib. Syst."},{"key":"ref_2","unstructured":"De Bernardinisa, L.P., Pinelloa, C., and Sgroia, A.L. (2005). Platform-based design for embedded systems. Embedded Systems Handbook, CRC Press. [1st ed.]."},{"key":"ref_3","doi-asserted-by":"crossref","first-page":"241439","DOI":"10.1155\/2012\/241439","article-title":"The chimera: An off-theshelf CPU\/GPGPU\/FPGA hybrid computing platform","volume":"2012","author":"Inta","year":"2012","journal-title":"Int. J. Reconfigurable Comput."},{"key":"ref_4","doi-asserted-by":"crossref","unstructured":"Putnam, A., Caulfield, A.M., Chung, E.S., Chiou, D., Constantinides, K., Demme, J., Esmaeilzadeh, H., Fowers, J., Gopal, G.P., and Gray, J. (2014, January 14\u201318). A reconfigurable fabric for accelerating large-scale datacenter services. Proceedings of the 2014 ACM\/IEEE 41st International Symposium on Computer Architecture (ISCA), Minneapolis, MN, USA.","DOI":"10.1109\/ISCA.2014.6853195"},{"key":"ref_5","unstructured":"Plessl, C., and Platzner, M. (2004). Virtualization of hardware-introduction and survey. ERSA, CSREA Press."},{"key":"ref_6","doi-asserted-by":"crossref","unstructured":"Vaishnav, A., Pham, K.D., and Koch, D. (2018, January 27\u201331). A survey on FPGA virtualization. Proceedings of the 2018 28th International Conference on Field Programmable Logic and Applications (FPL), Dublin, Ireland.","DOI":"10.1109\/FPL.2018.00031"},{"key":"ref_7","doi-asserted-by":"crossref","unstructured":"G\u00f6hringer, D., H\u00fcbner, M., Hugot-Derville, L., and Becker, J. (2010, January 19\u201322). Message passing interface support for the runtime adaptive multi-processor system-on-Chip RAMPSoC. Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, Samos, Greece.","DOI":"10.1109\/ICSAMOS.2010.5642043"},{"key":"ref_8","unstructured":"Shen, X., Wang, X., Zhu, Y., Huang, T., and Kong, X. (December, January 29). Implementing dynamic web page interactions with a Java processor core on FPGA. Proceedings of the Engineering and Industries (ICEI), 2nd International Conference on IEEE, Jeju, Korea."},{"key":"ref_9","doi-asserted-by":"crossref","first-page":"588","DOI":"10.1016\/j.micpro.2012.06.012","article-title":"A new heterogeneous tree-based application specific FPGA and its comparison with mesh-based application specific FPGA","volume":"36","author":"Farooq","year":"2012","journal-title":"Microprocess. Microsyst."},{"key":"ref_10","doi-asserted-by":"crossref","unstructured":"Chen, Y., Wang, Y., Ha, Y., Felipe, M.R., Ren, S., and Aung, K.M.M. (2013, January 9\u201311). sAES: A high throughput and low latency secure cloud storage with pipelined DMA based PCIe interface. Proceedings of the 2013 International Conference on Field-Programmable Technology (FPT), Kyoto, Japan.","DOI":"10.1109\/FPT.2013.6718391"},{"key":"ref_11","unstructured":"Xu, L., Shi, W., and Suh, T. (July, January 27). PFC: Privacy preserving FPGA cloud\u2014A case study of mapreduce. Proceedings of the IEEE International Conference on Cloud Computing, Anchorage, AK, USA."},{"key":"ref_12","doi-asserted-by":"crossref","unstructured":"Yang, H., and Yan, X. (2015, January 24\u201326). Memory coherency based CPU-Cache-FPGA acceleration architecture for cloud computing. Proceedings of the Information Science and Control Engineering (ICISCE), 2nd International Conference, Shanghai, China.","DOI":"10.1109\/ICISCE.2015.74"},{"key":"ref_13","doi-asserted-by":"crossref","unstructured":"Kidane, H.L., Bourennane, E.B., and Ochoa-Ruiz, G. (2016, January 21\u201323). Noc based virtualized accelerators for cloud computing. Proceedings of the IEEE 2016, 10th International Symposium on Embedded Multicore\/Many-core Systems-on-Chip (MCSOC), Lyon, France.","DOI":"10.1109\/MCSoC.2016.21"},{"key":"ref_14","doi-asserted-by":"crossref","unstructured":"Will, M.A., and Ko, R.K. (2017, January 1\u20134). Secure FPGA as a service\u2014Towards secure data processing by physicalizing the cloud. Proceedings of the IEEE Trustcom\/BigDataSE\/ICESS 2017, Sydney, NSW, Australia.","DOI":"10.1109\/Trustcom\/BigDataSE\/ICESS.2017.270"},{"key":"ref_15","doi-asserted-by":"crossref","unstructured":"Yazar, A., Erol, A., and Schmidt, E.G. (2018, January 2\u20135). ACCLOUD (Accelerated CLOUD): A novel FPGA-Accelerated cloud architecture. Proceedings of the 26th Signal Processing and Communications Applications (SIU), Izmir, Turkey.","DOI":"10.1109\/SIU.2018.8404548"},{"key":"ref_16","doi-asserted-by":"crossref","unstructured":"Mbongue, J., Hategekimana, F., Tchuinkou Kwadjo, D., Andrews, D., and Bobda, C. (2018, January 2\u20137). FPGAVirt: A Novel Virtualization Framework for FPGAs in the Cloud. Proceedings of the IEEE 11th International Conference on Cloud Computing, San Francisco, CA, USA.","DOI":"10.1109\/CLOUD.2018.00122"},{"key":"ref_17","doi-asserted-by":"crossref","first-page":"38009","DOI":"10.1109\/ACCESS.2019.2906910","article-title":"Cloud-based FPGA custom computing machines for streaming applications","volume":"7","author":"Elrabaa","year":"2019","journal-title":"IEEE Access"},{"key":"ref_18","doi-asserted-by":"crossref","first-page":"8085461","DOI":"10.1155\/2019\/8085461","article-title":"From FPGA to support cloud to cloud of FPGA: State of the art","volume":"2019","author":"Skhiri","year":"2019","journal-title":"Int. J. Reconfigurable Comput."},{"key":"ref_19","doi-asserted-by":"crossref","first-page":"339","DOI":"10.1007\/s10586-013-0280-9","article-title":"Direct GPU\/FPGA communication via PCI express","volume":"17","author":"Bittner","year":"2013","journal-title":"Cluster Comput."},{"key":"ref_20","doi-asserted-by":"crossref","first-page":"229","DOI":"10.14778\/1687627.1687654","article-title":"Streams on wires: A query compiler for FPGAS","volume":"2","author":"Mueller","year":"2009","journal-title":"Proc. VLDB Endow."},{"key":"ref_21","doi-asserted-by":"crossref","unstructured":"Dally, W.J., and Towles, B. (2001, January 18\u201322). Route packets, not wires: On-chip interconnection networks. Proceedings of the Design Automation Conference, Las Vegas, NV, USA.","DOI":"10.1145\/378239.379048"},{"key":"ref_22","doi-asserted-by":"crossref","first-page":"10497","DOI":"10.1109\/ACCESS.2018.2806618","article-title":"Interconnect solutions for virtualized field-programmable gate arrays","volume":"6","author":"Yazdanshenas","year":"2018","journal-title":"IEEE Access"},{"key":"ref_23","doi-asserted-by":"crossref","unstructured":"de Lima, O.A., Costa, W.N., Fresse, V., and Rousseau, F. (2016, January 7\u20139). A survey of NoC evaluation platforms on FPGAs. Proceedings of the International Conference on Field-Programmable Technology (FPT), Xi\u2019an, China.","DOI":"10.1109\/FPT.2016.7929538"},{"key":"ref_24","doi-asserted-by":"crossref","unstructured":"Kidane, H.L., Bourennane, E.B., and Ochoa-Ruiz, G. (2017, January 18\u201320). Run-time scalable noc for fpga based virtualized ips. Proceedings of the IEEE 11th International Symposium on Embedded Multicore\/Many-core Systems-on-Chip (MCSoC), Seoul, Korea.","DOI":"10.1109\/MCSoC.2017.32"},{"key":"ref_25","doi-asserted-by":"crossref","unstructured":"Kidane, H.L., and Bourennane, E.B. (2018, January 12\u201314). MARTE and IP-XACT based approach for run-time scalable NoC. Proceedings of the IEEE 12th International Symposium on Embedded Multicore\/Many-Core Systems-on-Chip (MCSoC), Hanoi, Vietnam.","DOI":"10.1109\/MCSoC2018.2018.00036"},{"key":"ref_26","doi-asserted-by":"crossref","first-page":"1241","DOI":"10.1080\/00207217.2010.512017","article-title":"Building a multi-FPGA-based emulation framework to support networks-on-chip design and verification","volume":"97","author":"Liu","year":"2010","journal-title":"Int. J. Electron."},{"key":"ref_27","doi-asserted-by":"crossref","unstructured":"Krishnaiah, G., Silpa, B.V., Panda, P.R., and Kumar, A. (2010, January 24\u201329). Fastfwd: An efficient hardware acceleration technique for trace-driven network-on-chip simulation. Proceedings of the eighth IEEE\/ACM\/IFIP International Conference on Hardware\/Software Codesign and System Synthesis, Scottsdale, AZ, USA.","DOI":"10.1145\/1878961.1879006"},{"key":"ref_28","doi-asserted-by":"crossref","unstructured":"Wang, C., Hu, W.H., Lee, S.E., and Bagherzadeh, N. (2010, January 17\u201319). Area and power-efficient innovative network on-chip architecture. Proceedings of the 2010 18th Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP), Pisa, Italy.","DOI":"10.1109\/PDP.2010.15"},{"key":"ref_29","doi-asserted-by":"crossref","unstructured":"Lotlikar, S., Pai, V., and Gratz, P. (2011, January 2\u20137). AcENoCs: A configurable HW\/SW platform for FPGA accelerated NoC emulation. Proceedings of the 24th Internatioal Conference on VLSI Design (VLSI Design), Chennai, India.","DOI":"10.1109\/VLSID.2011.46"},{"key":"ref_30","doi-asserted-by":"crossref","unstructured":"Papamichael, M.K. (2011, January 11\u201313). Fast scalable FPGA-based network-on-chip simulation models. Proceedings of the 2011 9th IEEE\/ACM Internatioal Conference on Formal Methods and Models for Codesign (MEMOCODE), Cambridge, UK.","DOI":"10.1109\/MEMCOD.2011.5970513"},{"key":"ref_31","doi-asserted-by":"crossref","unstructured":"Papamichael, M.K., Hoe, J.C., and Mutlu, O. (2011, January 1\u20134). Fist: A fast, lightweight, FPGA-friendly packet latency estimator for noc modeling in full-system simulations. Proceedings of the 2011 Fifth IEEE\/ACM International Symposium on Networks on Chip (NoCS), Pittsburgh, PA, USA.","DOI":"10.1145\/1999946.1999969"},{"key":"ref_32","doi-asserted-by":"crossref","unstructured":"Ku, W.-C., and Chen, T.-F. (2011, January 25\u201328). Accelerating manycore simulation by efficient noc interconnection partition on FPGA simulation platform. Proceedings of the 2011 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan.","DOI":"10.1109\/VDAT.2011.5783638"},{"key":"ref_33","doi-asserted-by":"crossref","unstructured":"Pellauer, M., Adler, M., Kinsy, M., Parashar, A., and Emer, J. (2011, January 12\u201316). Hasim: FPGA-based high-detail multicore simulation using time-division multiplexing. Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture (HPCA), San Antonio, TX, USA.","DOI":"10.1109\/HPCA.2011.5749747"},{"key":"ref_34","doi-asserted-by":"crossref","unstructured":"Tan, J., Fresse, V., and Rousseau, F. (2011, January 24\u201327). Generation of emulation platforms for NoC exploration on FPGA. Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping (RSP), Karlsruhe, Germany.","DOI":"10.1109\/RSP.2011.5929994"},{"key":"ref_35","doi-asserted-by":"crossref","unstructured":"Heck, G., Guazzelli, R., Moraes, F., Calazans, N., and Soares, R. (2012, January 20\u201323). HardNoC: A platform to validate networks on chip through FPGA prototyping. Proceedings of the VIII Southern Conference on Programmable Logic (SPL), Bento Goncalves, Spain.","DOI":"10.1109\/SPL.2012.6211781"},{"key":"ref_36","doi-asserted-by":"crossref","unstructured":"Fresse, V., Ge, Z., Tan, J., and Rousseau, F. (2012, January 11\u201312). Case study: Deployment of the 2d noc on 3d for the generation of large emulation platforms. Proceedings of the 2012 23rd IEEE International Symposium on Rapid System Prototyping (RSP), Tampere, Finland.","DOI":"10.1109\/RSP.2012.6380686"},{"key":"ref_37","doi-asserted-by":"crossref","unstructured":"van Chu, T., Sato, S., and Kise, K. (2014, January 23\u201325). Knocemu: High speed fpga emulator for kilo-node scale nocs. Embedded Multicore\/Manycore SoCs (MCSoc). Proceedings of the 2014 IEEE 8th International Symposium on Embedded Multicore\/Manycore SoCs, Aizu-Wakamatsu, Japan.","DOI":"10.1109\/MCSoC.2014.38"},{"key":"ref_38","doi-asserted-by":"crossref","unstructured":"de Lima, O.A., Fresse, V., and Rousseau, F. (, January 10\u201312). Evaluation of snmp-like protocol to manage a NOC emulation platform. Proceedings of the 2014 International Conference on Field-Programmable Technology (FPT), Shanghai, China.","DOI":"10.1109\/FPT.2014.7082776"},{"key":"ref_39","unstructured":"Kang, J.M., Bannazadeh, H., and Leon-Garcia, A. (2013, January 27\u201331). Savi testbed: Control and management of converged virtual ict resources. Proceedings of the IFIP\/IEEE International Symposium on Integrated Network Management, Ghent, Belgium."},{"key":"ref_40","unstructured":"(2019, December 02). Amazon Web Services EC2. FPGA Hardware and Software Development Kit. Available online: https:\/\/github.com\/aws\/aws-fpga."},{"key":"ref_41","doi-asserted-by":"crossref","unstructured":"Weerasinghe, J., Abel, F., Hagleitner, C., and Herkersdorf, A. (2015, January 10\u201314). Enabling FPGAs in hyperscale data centers. Proceedings of the 15th IEEE UIC-ATC-ScalCom, Beijing, China.","DOI":"10.1109\/UIC-ATC-ScalCom-CBDCom-IoP.2015.199"},{"key":"ref_42","unstructured":"(2020, March 23). Alveo Nimbix Cloud. Available online: https:\/\/www.nimbix.net\/alveotrial."},{"key":"ref_43","unstructured":"Voss, N., Quintana, P., Mencer, O., Luk, W., and Gaydadjiev, G. (May, January 28). Memory mapping for multi-die FPGAs. Proceedings of the IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), San Diego, CA, USA."},{"key":"ref_44","doi-asserted-by":"crossref","unstructured":"Voss, N., Girdlestone, S., Becker, T., Mencer, O., Luk, W., and Gaydadjiev, G. (2019, January 9\u201311). Low area overhead custom buffering for FFT. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), Cancun, Mexico.","DOI":"10.1109\/ReConFig48160.2019.8994775"},{"key":"ref_45","doi-asserted-by":"crossref","first-page":"54","DOI":"10.1145\/3339861","article-title":"Time-multiplexed FPGA overlay architectures: A survey","volume":"24","author":"Li","year":"2019","journal-title":"ACM Trans. Des. Autom. Electron. Syst."},{"key":"ref_46","unstructured":"Jain, A.K. (2017). Architecture Centric Coarse-Grained FPGA Overlays. [Ph.D. Thesis, Nanyang Technological University]."},{"key":"ref_47","doi-asserted-by":"crossref","unstructured":"Cheah, H.Y., Fahmy, S.A., and Maskell, D.L. (2012, January 10\u201312). iDEA: A DSP block-based FPGA Soft Processor. Proceedings of the 2012 International Conference on Field-Programmable Technology (FPT), Seoul, Korea.","DOI":"10.1109\/FPT.2012.6412128"},{"key":"ref_48","unstructured":"(2019, December 03). Xilinx MicroBlaze Soft Processor Core. Available online: https:\/\/www.xilinx.com\/products\/design-tools\/microblaze.html."},{"key":"ref_49","unstructured":"(2019, December 04). Altera Nios II Processor. Available online: https:\/\/www.altera.com\/products\/processors\/overview.html."},{"key":"ref_50","unstructured":"Severance, A., and Lemieux, G.G.F. (October, January 29). Embedded supercomputing in FPGAs with the VectorBlox MXP matrix processor. Proceedings of the International Conference on Hardware\/Software Codesign and System Synthesis, Montreal, QC, Canada."},{"key":"ref_51","doi-asserted-by":"crossref","unstructured":"Severance, A., and Lemieux, G. (2011, January 17\u201319). VENICE: A compact vector processor for FPGA Applications. Proceedings of the 2011 IEEE Hot Chips 23 Symposium (HCS), Stanford, CA, USA.","DOI":"10.1109\/HOTCHIPS.2011.7477515"},{"key":"ref_52","doi-asserted-by":"crossref","unstructured":"Chou, C.H., Severance, A., Brant, A.D., Liu, Z., Sant, S., and Lemieux, G.G. (March, January 27). VEGAS: Soft vector processor with scratchpad memory. Proceedings of the 19th ACM\/SIGDA international symposium on Field programmable gate arrays 2011, Monterey, CA, USA.","DOI":"10.1145\/1950413.1950420"},{"key":"ref_53","doi-asserted-by":"crossref","unstructured":"Yiannacouras, P., Steffan, J.G., and Rose, J. (2008, January 19\u201324). VESPA: Portable, scalable, and flexible FPGA-based vector processors. Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems, Atlanta, GA, USA.","DOI":"10.1145\/1450095.1450107"},{"key":"ref_54","doi-asserted-by":"crossref","unstructured":"Yu, J., Lemieux, G., and Eagleston, C. (2008, January 24\u201326). Vector Processing as a Soft-core CPU Accelerator. Proceedings of the 16th International ACM\/SIGDA Symposium on Field Programmable Gate Arrays, Monterey, CA, USA.","DOI":"10.1145\/1344671.1344704"},{"key":"ref_55","doi-asserted-by":"crossref","unstructured":"Cong, J., Huang, H., Ma, C., Xiao, B., and Zhou, P. (2014, January 11\u201313). A fully pipelined and dynamically composable architecture of CGRA. Proceedings of the 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines, Boston, MA, USA.","DOI":"10.1109\/FCCM.2014.12"},{"key":"ref_56","doi-asserted-by":"crossref","unstructured":"Shukla, S., Bergmann, N.W., and Becker, J. (2007, January 26\u201330). QUKU: A FPGA based flexible coarse grain architecture design paradigm using process networks. Proceedings of the 2007 IEEE International Parallel and Distributed Processing Symposium, Rome, Italy.","DOI":"10.1109\/IPDPS.2007.370382"},{"key":"ref_57","doi-asserted-by":"crossref","unstructured":"Landy, A., and Stitt, G. (2012, January 7\u201312). A low-overhead interconnect architecture for virtual reconfigurable fabrics. Proceedings of the 2012 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, Tampere, Finland.","DOI":"10.1145\/2380403.2380427"},{"key":"ref_58","doi-asserted-by":"crossref","first-page":"42","DOI":"10.1109\/MM.2013.108","article-title":"Fast, flexible high-level synthesis from OpenCL using reconfiguration contexts","volume":"34","author":"Coole","year":"2014","journal-title":"IEEE Micro"},{"key":"ref_59","doi-asserted-by":"crossref","first-page":"38","DOI":"10.1109\/MM.2012.51","article-title":"DySER: Unifying functionality and parallelism specialization for energy-efficient computing","volume":"32","author":"Govindaraju","year":"2012","journal-title":"IEEE Micro"},{"key":"ref_60","doi-asserted-by":"crossref","unstructured":"So, H.K.-H., and Liu, C. (2016). FPGA Overlays. FPGAs for Software Programmers, Springer.","DOI":"10.1007\/978-3-319-26408-0_16"},{"key":"ref_61","unstructured":"Brant, A.D. (2012). Coarse and Fine Grain Programmable Overlay Architectures for FPGAs. [MSc Thesis, University of British Columbia]."},{"key":"ref_62","doi-asserted-by":"crossref","unstructured":"Rashid, R., Steffan, J.G., and Betz, V. (2014, January 10\u201312). Comparing performance, productivity and scalability of the TILT overlay processor to OpenCL HLS. Proceedings of the 2014 International Conference on Field-Programmable Technology (FPT), Shanghai, China.","DOI":"10.1109\/FPT.2014.7082748"},{"key":"ref_63","doi-asserted-by":"crossref","unstructured":"Paul, K., Dash, C., and Moghaddam, M.S. (2012, January 5\u20138). reMORPH: A runtime reconfigurable architecture. Proceedings of the 2012 15th Euromicro Conference on Digital System Design, Cesme, Izmir, Turkey.","DOI":"10.1109\/DSD.2012.111"},{"key":"ref_64","doi-asserted-by":"crossref","unstructured":"Kapre, N., Mehta, N., Delorimier, M., Rubin, R., Barnor, H., Wilson, M.J., Wrighton, M., and DeHon, A. (2006, January 24\u201326). Packet switched vs. time multiplexed FPGA overlay networks. Proceedings of the 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, CA, USA.","DOI":"10.1109\/FCCM.2006.55"},{"key":"ref_65","doi-asserted-by":"crossref","unstructured":"Papamichael, M.K., and Hoe, J.C. (2012, January 22\u201324). CONNECT: Re-examining conventional wisdom for designing nocs in the context of FPGAs. Proceedings of the ACM\/SIGDA International Symposium on Field Programmable Gate Arrays 2012, Monterey, CA, USA.","DOI":"10.1145\/2145694.2145703"},{"key":"ref_66","doi-asserted-by":"crossref","unstructured":"Huan, Y., and DeHon, A. (2012, January 10\u201312). FPGA optimized packet-switched NoC using split and merge primitives. Proceedings of the 2012 International Conference on Field-Programmable Technology, Seoul, Korea.","DOI":"10.1109\/FPT.2012.6412110"},{"key":"ref_67","doi-asserted-by":"crossref","unstructured":"Kapre, N., and Gray, J. (2015, January 2\u20134). Hoplite: Building austere overlay NoCs for FPGAs. Proceedings of the 2015 25th International Conference on Field Programmable Logic and Applications (FPL), London, UK.","DOI":"10.1109\/FPL.2015.7293956"},{"key":"ref_68","doi-asserted-by":"crossref","unstructured":"Brant, A., and Lemieux, G.G.F. (May, January 29). ZUMA: An open FPGA overlay architecture. Proceedings of the 2012 IEEE 20th international symposium on field-programmable custom computing machines, Toronto, ON, Canada.","DOI":"10.1109\/FCCM.2012.25"},{"key":"ref_69","doi-asserted-by":"crossref","unstructured":"Ferreira, R., Vendramini, J.G., Mucida, L., Pereira, M.M., and Carro, L. (2011, January 9\u201314). An FPGA-based heterogeneous coarse-grained dynamically reconfigurable architecture. Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems, Taipei, Taiwan.","DOI":"10.1145\/2038698.2038728"},{"key":"ref_70","doi-asserted-by":"crossref","unstructured":"Kinsy, M.A., Pellauer, M., and Devadas, S. (2011, January 5\u20137). Heracles: Fully synthesizable parameterized mips based multicore system. Proceedings of the 21st International Conference on Field Programmable Logic and Applications, Chania, Greece.","DOI":"10.1109\/FPL.2011.70"},{"key":"ref_71","unstructured":"Liu, C., Yu, C.L., and So, H.K. (2013, January 28\u201330). A soft coarse-grained reconfigurable array based high-level synthesis methodology: Promoting design productivity and exploring extreme FPGA frequency. Proceedings of the IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines, Seattle, WA, USA."},{"key":"ref_72","doi-asserted-by":"crossref","unstructured":"Gray, J. (2016, January 1\u20133). GRVI-phalanx: A massively parallel RISC-V FPGA accelerator. Proceedings of the IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines, Washington, DC, USA.","DOI":"10.1109\/FCCM.2016.12"},{"key":"ref_73","unstructured":"Li, X., Jain, A., Maskell, D., and Fahmy, S.A. (2016, January 21\u201323). An area-efficient FPGA overlay using DSP block based time-multiplexed functional units. Proceedings of the 2nd International Workshop on Overlay Architectures for FPGAs, Monterey, CA, USA."},{"key":"ref_74","doi-asserted-by":"crossref","unstructured":"Kumar, H.B.C., Ravi, P., Modi, G., and Kapre, N. (2017, January 22\u201324). 120-core microAptiv MIPS overlay for the Terasic DE5-NET FPGA board. Proceedings of the ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA.","DOI":"10.1145\/3020078.3021751"},{"key":"ref_75","doi-asserted-by":"crossref","unstructured":"Byma, S., Steffan, J.G., Bannazadeh, H., Garcia, A.L., and Chow, P. (2014, January 11\u201313). FPGAs in the cloud: Booting virtualized hardware accelerators with OpenStack. Proceedings of the 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines, Boston, MA, USA.","DOI":"10.1109\/FCCM.2014.42"},{"key":"ref_76","doi-asserted-by":"crossref","unstructured":"Fahmy, S.A., Vipin, K., and Shreejith, S. (December, January 30). Virtualized FPGA accelerators for efficient cloud computing. Proceedings of the 2015 IEEE 7th International Conference on Cloud Computing Technology and Science (CloudCom), Vancouver, BC, Canada.","DOI":"10.1109\/CloudCom.2015.60"},{"key":"ref_77","doi-asserted-by":"crossref","unstructured":"Tarafdar, N., Lin, T., Fukuda, E., Bannazadeh, H., Leon-Garcia, A., and Chow, P. (2017, January 22\u201324). Enabling flexible network FPGA clusters in a heterogeneous cloud data center. Proceedings of the 2017 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA \u201917), Monterey, CA, USA.","DOI":"10.1145\/3020078.3021742"},{"key":"ref_78","unstructured":"Knodel, O., Genssler, P.R., and Spallek, R.G. (2017, January 10\u201314). Virtualizing reconfigurable hardware to provide scalability in cloud architectures. Proceedings of the Tenth International Conference on Advances in Circuits, Electronics and Micro-electronics (CENICS 2017), Rome, Italy."},{"key":"ref_79","doi-asserted-by":"crossref","unstructured":"Zhang, J., Xiong, Y., Xu, N., Shu, R., Li, B., Cheng, P., Chen, G., and Moscibroda, T. (2017, January 2). The feniks FPGA operating system for cloud computing. Proceedings of the 8th Asia-Pacific Workshop on Systems, Mumbai, India.","DOI":"10.1145\/3124680.3124743"},{"key":"ref_80","doi-asserted-by":"crossref","unstructured":"Abbani, N., Ali, A., Doa\u2019A, A.O., Jomaa, M., Sharafeddine, M., Artail, H., Akkary, H., Saghir, M.A., Awad, M., and Hajj, H. (2011, January 2\u20134). A distributed reconfigurable active SSD platform for data intensive applications. Proceedings of the 2011 IEEE International Conference on High Performance Computing and Communications, Banff, AB, Canada.","DOI":"10.1109\/HPCC.2011.14"},{"key":"ref_81","unstructured":"Wang, W. (October, January 29). pvFPGA: Accessing an FPGA-based hardware accelerator in a paravirtualized environment. Proceedings of the 2013 International Conference on Hardware\/Software Codesign and System Synthesis (CODES+ ISSS), Montreal, QC, Canada."},{"key":"ref_82","doi-asserted-by":"crossref","unstructured":"Xia, T., Pr\u00e9votet, J.C., and Nouvel, F. (2016, January 7\u20139). Hypervisor mechanisms to manage FPGA reconfigurable accelerators. Proceedings of the 2016 International Conference on Field-Programmable Technology (FPT), Xi\u2019an, China.","DOI":"10.1109\/FPT.2016.7929187"},{"key":"ref_83","doi-asserted-by":"crossref","first-page":"61","DOI":"10.1007\/s11265-014-0884-1","article-title":"Virtualized execution and management of hardware tasks on a hybrid ARM-FPGA platform","volume":"77","author":"Jain","year":"2014","journal-title":"J. Signal Process. Syst."},{"key":"ref_84","doi-asserted-by":"crossref","unstructured":"Chen, F., Shan, Y., Zhang, Y., Wang, Y., Franke, H., Chang, X., and Wang, K. (2014, January 20\u201322). Enabling FPGAs in the cloud. Proceedings of the 11th ACM Conference on Computing Frontiers, Cagliari, Italy.","DOI":"10.1145\/2597917.2597929"},{"key":"ref_85","unstructured":"Bobda, C., Majer, A., Ahmadinia, A., Haller, T., Linarth, A., and Teich, J. (2005, January 11\u201314). The erlangen slot machine: Increasing flexibility in FPGA-based reconfigurable platforms. Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, Singapore."},{"key":"ref_86","doi-asserted-by":"crossref","first-page":"335","DOI":"10.1587\/transinf.2017RCP0004","article-title":"Enabling FPGA-as-a-service in the cloud with hCODE platform","volume":"101","author":"Zhao","year":"2018","journal-title":"IEICE Trans. Inf. Syst."},{"key":"ref_87","doi-asserted-by":"crossref","unstructured":"Weerasinghe, J., Polig, R., Abel, F., and Hagleitner, C. (2016, January 7\u20139). Network-attached FPGAs for data center applications. Proceedings of the 2016 International Conference on Field-Programmable Technology (FPT), Xi\u2019an, China.","DOI":"10.1109\/FPT.2016.7929186"},{"key":"ref_88","doi-asserted-by":"crossref","first-page":"23","DOI":"10.1109\/MDAT.2017.2748393","article-title":"Designing for FPGAs in the Cloud","volume":"35","author":"Tarafdar","year":"2017","journal-title":"IEEE Des. Test"},{"key":"ref_89","doi-asserted-by":"crossref","first-page":"1900","DOI":"10.1109\/ACCESS.2017.2661582","article-title":"Virtualized execution runtime for FPGA accelerators in the cloud","volume":"5","author":"Asiatici","year":"2017","journal-title":"IEEE Access"},{"key":"ref_90","doi-asserted-by":"crossref","first-page":"24","DOI":"10.1109\/MCC.2015.51","article-title":"Containerization and the PaaS cloud","volume":"2","author":"Pahl","year":"2015","journal-title":"IEEE Cloud Comput."},{"key":"ref_91","doi-asserted-by":"crossref","unstructured":"Kirchgessner, R., Stitt, G., George, A., and Lam, H. (2012, January 22\u201324). VirtualRC: A virtual FPGA platform for applications and tools portability. Proceedings of the ACM\/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA\u201912), ACM, Monterey, CA, USA.","DOI":"10.1145\/2145694.2145728"},{"key":"ref_92","doi-asserted-by":"crossref","unstructured":"Asghari, M., Rajabzadeh, A., and Dashtbani, M. (2016, January 20\u201321). HFIaaS: A proposed FPGA infrastructure as a service framework using high-level synthesis. Proceedings of the 6th International Conference on Computer and Knowledge Engineering (ICCKE), Mashhad, Iran.","DOI":"10.1109\/ICCKE.2016.7802118"},{"key":"ref_93","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1016\/j.sysarc.2017.06.001","article-title":"Extended overlay architectures for heterogeneous FPGA cluster management","volume":"78","author":"Najem","year":"2017","journal-title":"J. Syst. Archit."},{"key":"ref_94","doi-asserted-by":"crossref","unstructured":"Eskandari, N., Tarafdar, N., Ly-Ma, D., and Chow, P. (2019, January 24\u201326). A modular heterogeneous stack for deploying FPGAs and CPUs in the data center. Proceedings of the 2019 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays, Seaside, CA, USA.","DOI":"10.1145\/3289602.3293909"},{"key":"ref_95","doi-asserted-by":"crossref","unstructured":"Vaishnav, A., Pham, K.D., Manev, K., and Koch, D. (2019, January 8\u201312). The FOS (FPGA Operating System) Demo. Proceedings of the 29th International Conference on Field Programmable Logic and Application (FPL), Barcelona, Spain.","DOI":"10.1109\/FPL.2019.00081"},{"key":"ref_96","unstructured":"(2020, March 24). Intel OPAE. Available online: http:\/\/01.org\/OPAE."},{"key":"ref_97","doi-asserted-by":"crossref","unstructured":"Yazdanshenas, S., and Betz, V. (2017, January 4\u20138). Quantifying and mitigating the costs of FPGA virtualization. Proceedings of the 27th International Conference on Field Programmable Logic and Applications (FPL), Ghent, Belgium.","DOI":"10.23919\/FPL.2017.8056807"},{"key":"ref_98","doi-asserted-by":"crossref","unstructured":"Happe, M., Traber, A., and Keller, A. (2015). Preemptive hardware multitasking in ReconOS. Applied Reconfigurable Computing, Springer.","DOI":"10.1007\/978-3-319-16214-0_7"},{"key":"ref_99","doi-asserted-by":"crossref","unstructured":"Rupnow, K., Fu, W., and Compton, K. (2009, January 5\u20137). Block, drop or roll(back): Alternative preemption methods for RH multi-tasking. Proceedings of the 17th IEEE Symposium on Field Programmable Custom Computing Machines, Napa, CA, USA.","DOI":"10.1109\/FCCM.2009.30"},{"key":"ref_100","first-page":"1","article-title":"Generating efficient context-switch capable circuits through autonomous design flow","volume":"10","author":"Bourge","year":"2016","journal-title":"ACM TRETS"},{"key":"ref_101","doi-asserted-by":"crossref","unstructured":"Lubbers, E., and Platzner, M. (2007, January 27\u201329). ReconOS: An RTOS supporting hard-and software threads. Proceedings of the 2007 International Conference on Field Programmable Logic and Applications, Amsterdam, Netherlands.","DOI":"10.1109\/FPL.2007.4380686"},{"key":"ref_102","doi-asserted-by":"crossref","unstructured":"Peck, W., Anderson, E., Agron, J., Stevens, J., Baijot, F., and Andrews, D. (2006, January 28\u201330). Hthreads: A computational model for reconfigurable devices. Proceedings of the 2006 International Conference on Field Programmable Logic and Applications, Madrid, Spain.","DOI":"10.1109\/FPL.2006.311336"},{"key":"ref_103","doi-asserted-by":"crossref","unstructured":"Shan, Y., Wang, B., Yan, J., Wang, Y., Xu, N., and Yang, H. (2010, January 21\u201323). FPMR: MapReduce framework on FPGA. Proceedings of the 18th annual ACM\/SIGDA international symposium on Field programmable gate arrays 2010, Monterey, CA, USA.","DOI":"10.1145\/1723112.1723129"},{"key":"ref_104","doi-asserted-by":"crossref","unstructured":"Chen, Y.T., Cong, J., Fang, Z., Lei, J., and Wei, P. (2016, January 1\u20133). When spark meets FPGAs: A case study for next generation DNA sequencing acceleration. Proceedings of the 24th FCCM, Washington, DC, USA.","DOI":"10.1109\/FCCM.2016.18"},{"key":"ref_105","doi-asserted-by":"crossref","unstructured":"Mavridis, S., Pavlidakis, M., Stamoulias, I., Kozanitis, C., Chrysos, N., Kachris, C., Soudris, D., and Bilas, A. (2017, January 4\u20138). VineTalk: Simplifying software access and sharing of FPGAs in datacenters. Proceedings of the 27th International Conference on Field Programmable Logic and Applications (FPL), Ghent, Belgium.","DOI":"10.23919\/FPL.2017.8056788"},{"key":"ref_106","doi-asserted-by":"crossref","unstructured":"Eguro, K. (2010, January 2\u20134). SIRC: An extensible reconfigurable computing communication API. Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM, Charlotte, NC, USA.","DOI":"10.1109\/FCCM.2010.29"},{"key":"ref_107","unstructured":"(2020, March 23). Intel FPGA. SDK for OpenCL. Programming Guide. UG-OCL002. Available online: https:\/\/www.intel.com\/content\/dam\/www\/programmable\/us\/en\/pdfs\/literature\/hb\/opencl-sdk\/archives\/ug-aocl-programming-guide-16.1.pdf."},{"key":"ref_108","unstructured":"Segal, O., Colangelo, P., Nasiri, N., Qian, Z., and Margala, M. (2015). SparkCL: A unified programming framework for accelerators on heterogeneous clusters. arXiv."},{"key":"ref_109","doi-asserted-by":"crossref","unstructured":"Kulp, J., Siegel, S., and Miller, J. (2013). Open Component Portability Infrastructure (OPENCPI), Mercury Federal Systems Inc.. Technial Report.","DOI":"10.21236\/ADA580701"},{"key":"ref_110","unstructured":"(2020, March 24). Intel HLS Compiler: Fast Design, Coding and Hardware. Available online: https:\/\/www.intel.com\/content\/www\/us\/en\/software\/programmable\/quartus-prime\/hls-compiler.html."},{"key":"ref_111","unstructured":"(2020, March 24). Vivado High-Level Synthesis: Accelerates IP Creation by Enabling C, C++ and System C Specifications. Available online: https:\/\/www.xilinx.com\/products\/design-tools\/vivado\/integration\/esl-design.html."},{"key":"ref_112","unstructured":"(2020, March 24). Open Spatial Programming Language (OpenSPL), Maxeler Technologies. Available online: https:\/\/www.maxeler.com\/openspl-announced\/."},{"key":"ref_113","doi-asserted-by":"crossref","unstructured":"Pell, O., Mencer, O., Tsoi, K.H., and Luk, W. (2012). Maximum performance computing with dataflow engines. Computing in Science & Engineering, IEEE.","DOI":"10.1007\/978-1-4614-1791-0_25"},{"key":"ref_114","doi-asserted-by":"crossref","unstructured":"Fleming, K., and Adler, M. (2016). The LEAP FPGA Operating System. FPGAs for Software Programmers, Springer.","DOI":"10.1007\/978-3-319-26408-0_14"},{"key":"ref_115","doi-asserted-by":"crossref","unstructured":"Vesper, M., Koch, D., Vipin, K., and Fahmy, S.A. (September, January 29). JetStream: An open-source high-performance PCI express 3 streaming library for FPGA-to-Host and FPGA-to-FPGA communication. Proceedings of the 2016 26th international conference on field programmable logic and applications (FPL), Lausanne, Switzerland.","DOI":"10.1109\/FPL.2016.7577334"},{"key":"ref_116","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2815631","article-title":"RIFFA 2.1: A reusable integration framework for FPGA accelerators","volume":"8","author":"Jacobsen","year":"2015","journal-title":"ACM TRETS"},{"key":"ref_117","doi-asserted-by":"crossref","unstructured":"Yoshimi, M., Nishikawa, Y., Miki, M., Hiroyasu, T., Amano, H., and Mencer, O. (2010, January 17\u201319). A performance evaluation of CUBE: One Dimensional 512 FPGA cluster. Proceedings of the International Symposium on Applied Reconfigurable Computing, ARC 2010, Bangkok, Thailand.","DOI":"10.1007\/978-3-642-12133-3_36"},{"key":"ref_118","doi-asserted-by":"crossref","first-page":"3547","DOI":"10.1109\/TPDS.2016.2537805","article-title":"Melia: A MapReduce framework on OpenCL-Based FPGAs","volume":"27","author":"Wang","year":"2016","journal-title":"IEEE Trans. Parallel Distrib. Syst."},{"key":"ref_119","doi-asserted-by":"crossref","unstructured":"Yeung, J.H.C. (2008, January 14\u201315). Map-reduce as a programming model for custom computing machines. Proceedings of the 2008 16th International Symposium on Field-Programmable Custom Computing Machines, Palo Alto, CA, USA.","DOI":"10.1109\/FCCM.2008.19"},{"key":"ref_120","doi-asserted-by":"crossref","unstructured":"Tsoi, K.H., and Luk, W. (2010, January 21\u201323). Axel: A Heterogeneous Cluster with FPGAs and GPUs. Proceedings of the 18th Annual ACM\/SIGDA International Symposium on Field Programmable Gate Arrays 2010, Monterey, CA, USA.","DOI":"10.1145\/1723112.1723134"},{"key":"ref_121","doi-asserted-by":"crossref","unstructured":"Iordache, A., Pierre, G., Sanders, P., de FCoutinho, J.G., and Stillwell, M. (2016, January 6\u20139). High performance in the cloud with FPGA groups. Proceedings of the 9th International Conference on Utility and Cloud Computing, Shanghai, China.","DOI":"10.1145\/2996890.2996895"},{"key":"ref_122","doi-asserted-by":"crossref","unstructured":"Huang, M. (2016, January 5\u20137). Programming and runtime support to blaze FPGA accelerator deployment at datacenter scale. Proceedings of the Seventh ACM Symposium on Cloud Computing, SoCC \u201916, Santa Clara, CA, USA.","DOI":"10.1145\/2987550.2987569"},{"key":"ref_123","doi-asserted-by":"crossref","unstructured":"Theodoropoulos, D., Alachiotis, N., and Pnevmatikatos, D. (May, January 30). Multi-FPGA evaluation platform for disaggregated computing. Proceedings of the 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa, CA, USA.","DOI":"10.1109\/FCCM.2017.20"},{"key":"ref_124","unstructured":"Ouyang, J., Lin, S., Qi, W., Wang, Y., Yu, B., and Jiang, S. (2014, January 10\u201312). SDA: Software-defined accelerator for large-scale DNN systems. Proceedings of the IEEE Hot Chips 26 Symposium (HCS), Cupertino, CA, USA."},{"key":"ref_125","doi-asserted-by":"crossref","unstructured":"El-Araby, E., Gonzalez, I., and El-Ghazawi, T. (2008, January 17). Virtualizing and sharing reconfigurable resources in high-performance reconfigurable computing systems. Proceedings of the 2008 Second International Workshop on High-Performance Reconfigurable Computing Technology and Applications, Austin, TX, USA.","DOI":"10.1109\/HPRCTA.2008.4745683"},{"key":"ref_126","doi-asserted-by":"crossref","unstructured":"Zheng, Z., Wang, T., Weng, J., Mumtaz, S., Bashir, A.K., and Hussain, C.S. (2019). Differentially private high-dimensional data publication in internet of things. IEEE Internet Things J.","DOI":"10.1109\/JIOT.2019.2955503"},{"key":"ref_127","first-page":"261","article-title":"A distributed virtual data center network architecture for the future internet","volume":"114","author":"Bashir","year":"2015","journal-title":"IEICE Tech. Rep. (IN2014\u2013165)"},{"key":"ref_128","doi-asserted-by":"crossref","unstructured":"Bashir, A.K., Ohsita, Y., and Murata, M. (2016, January 27\u201330). Abstraction layer based virtual data center architecture for network function chaining. Proceedings of the International Conference on Distributed Computing Systems Workshops (ICDCSW)\u2014ICDCS, Nara, Japan.","DOI":"10.1109\/ICDCSW.2016.42"},{"key":"ref_129","unstructured":"Bashir, A.K., Ohsita, Y., and Murata, M. (2015, January 22\u201327). Abstraction layer based distributed architecture for virtualized data centers. Proceedings of the Cloud Computing 2015: 6th International Conference on Cloud Computing, Grids, and Virtualization, Nice, France."},{"key":"ref_130","doi-asserted-by":"crossref","unstructured":"Flynn, M.J. (2011). Flynn\u2019s taxonomy. Encycl. Parallel Comput., 689\u2013697.","DOI":"10.1007\/978-0-387-09766-4_2"},{"key":"ref_131","doi-asserted-by":"crossref","unstructured":"Caldeira, P., Penha, J.C., Bragan\u00e7a, L., Ferreira, R., Nacif, J.A., Ferreira, R., and Pereira, F.M. (2018, January 24\u201327). From Java to FPGA: An experience with the intel HARP system. Proceedings of the 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Lyon, France.","DOI":"10.1109\/CAHPC.2018.8645951"},{"key":"ref_132","doi-asserted-by":"crossref","unstructured":"Feng, L., Zhao, J., Liang, T., Sinha, S., and Zhang, W. (2019, January 2\u20136). LAMA: Link-Aware Hybrid Management for Memory Accesses in Emerging CPU-FPGA Platforms. Proceedings of the 56th ACM\/IEEE Design Automation Conference, Las Vegas, NV, USA.","DOI":"10.1145\/3316781.3317846"}],"container-title":["Future Internet"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/1999-5903\/12\/4\/64\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,6,26]],"date-time":"2024-06-26T13:41:59Z","timestamp":1719409319000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/1999-5903\/12\/4\/64"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,4,6]]},"references-count":132,"journal-issue":{"issue":"4","published-online":{"date-parts":[[2020,4]]}},"alternative-id":["fi12040064"],"URL":"https:\/\/doi.org\/10.3390\/fi12040064","relation":{},"ISSN":["1999-5903"],"issn-type":[{"value":"1999-5903","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,4,6]]}}}
