{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T06:56:26Z","timestamp":1648796186157},"reference-count":6,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"19","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2013]]},"DOI":"10.1587\/elex.10.20130571","type":"journal-article","created":{"date-parts":[[2013,9,9]],"date-time":"2013-09-09T23:20:16Z","timestamp":1378768816000},"page":"20130571-20130571","source":"Crossref","is-referenced-by-count":0,"title":["Low-power pipelined phase accumulator using CMOS-CML hybrid F\/Fs for pre-skewing operation"],"prefix":"10.1587","volume":"10","author":[{"given":"Yun-Hwan","family":"Jung","sequence":"first","affiliation":[{"name":"School of Electrical and Electronics Engineering, Chung-Ang University"}]},{"given":"Yong Sin","family":"Kim","sequence":"additional","affiliation":[{"name":"School of Electrical and Electronics Engineering, Chung-Ang University"}]},{"given":"Yohan","family":"Hong","sequence":"additional","affiliation":[{"name":"School of Electrical and Electronics Engineering, Chung-Ang University"}]},{"given":"Ju Eon","family":"Kim","sequence":"additional","affiliation":[{"name":"School of Electrical and Electronics Engineering, Chung-Ang University"}]},{"given":"Kwang-Hyun","family":"Baek","sequence":"additional","affiliation":[{"name":"School of Electrical and Electronics Engineering, Chung-Ang University"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] H. C. Yeoh, J.-H. Jung, Y.-H. Jung, and K.-H. Baek, “A 1.3-GHz 350-mW Hybrid Direct Digital Frequency Synthesizer in 90-nm CMOS,” IEEE J. Solid-State Circuits<\/i>, vol. 45, no. 9, pp. 1845-1855, Sep. 2010."},{"key":"2","unstructured":"[2] C.-Y. Yang, J.-H. Weng, and H.-Y. Chang, “A 5-GHz Direct Digital Frequency Synthesizer Using an Analog-Sine-Mapping Technique in 0.35-um SiGe BiCMOS,” IEEE J. Solid-State Circuits<\/i>, vol. 46, no. 9, pp. 2064-2072, Sep. 2011."},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] Y. S. Kim and S.-M. Kang, “A High Speed Low-Power Accumulator for Direct Digital Frequency Synthesizer,” Dig. IEEE MTT-s Int. Symp. Microwave, San Francisco, CA, USA<\/i>, pp. 502-505, Jun. 2006.","DOI":"10.1109\/MWSYM.2006.249620"},{"key":"4","unstructured":"[4] T. Yoo, S.-J. Cho, J. W. Lee, and K.-H. Baek, “Low-power fast-update pipelined phase accumulator for CML-based high-speed CMOS DDFSs,” IET Electronics letters<\/i>, vol. 48, no. 18, pp. 1102-1104, Aug. 2012."},{"key":"5","unstructured":"[5] Y.-H. Jung, T. Yoo, S.-J. Cho, and K.-H. Baek, “Pipelined phase accumulator using sequential FCW loading scheme for DDFSs,” IET Electronics letters<\/i>, vol. 48, no. 17, pp. 1044-1046, Aug. 2012."},{"key":"6","unstructured":"[6] P. Heydari and R. Mohanavelu, “Design of Ultrahigh-Speed Low-Voltage CMOS CML Buffers and Latches,” IEEE Trans. VLSI Syst.<\/i>, vol. 12, no. 10, pp. 1081-1093, Oct. 2004."}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/10\/19\/10_10.20130571\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,4,23]],"date-time":"2021-04-23T18:00:31Z","timestamp":1619200831000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/10\/19\/10_10.20130571\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013]]},"references-count":6,"journal-issue":{"issue":"19","published-print":{"date-parts":[[2013]]}},"URL":"http:\/\/dx.doi.org\/10.1587\/elex.10.20130571","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013]]}}}
