{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,3,26]],"date-time":"2024-03-26T18:49:17Z","timestamp":1711478957492},"reference-count":11,"publisher":"Hindawi Limited","license":[{"start":{"date-parts":[[2010,1,1]],"date-time":"2010-01-01T00:00:00Z","timestamp":1262304000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"DOI":"10.13039\/501100001665","name":"French National Research Agency","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100001665","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["International Journal of Reconfigurable Computing"],"published-print":{"date-parts":[[2010]]},"abstract":"The dynamic and partial reconfiguration of FPGAs enables the dynamic placement in reconfigurable zones of the tasks that describe an application. However, the dynamic management of the tasks impacts the communications since tasks are not present in the FPGA during all computation time. So, the task manager should ensure the allocation of each new task and their interconnection which is performed by a flexible interconnection network. In this article, various communication architectures, in particular interconnection networks, are studied. Each architecture is evaluated with respect to its suitability for the paradigm of the dynamic and partial reconfiguration in FPGA implementations. This study leads us to propose the DRAFT network that supports the communication constraints into the context of dynamic reconfiguration. We also present DRAGOON, the automatic generator of networks, which allows to implement and to simulate the DRAFT topology. Finally, DRAFT and the two most popular Networks-on-Chip are implemented in several configurations using DRAGOON, and compared considering real implementation results.<\/jats:p>","DOI":"10.1155\/2010\/390545","type":"journal-article","created":{"date-parts":[[2010,3,1]],"date-time":"2010-03-01T15:29:06Z","timestamp":1267457346000},"page":"1-15","source":"Crossref","is-referenced-by-count":11,"title":["Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures"],"prefix":"10.1155","volume":"2010","author":[{"given":"Ludovic","family":"Devaux","sequence":"first","affiliation":[{"name":"IRISA, Universit\u00e9 de Rennes, 6 rue de Kerampont, BP 80518, 22302 Lannion, France"}]},{"given":"Sana","family":"Ben Sassi","sequence":"additional","affiliation":[{"name":"IRISA, Universit\u00e9 de Rennes, 6 rue de Kerampont, BP 80518, 22302 Lannion, France"}]},{"given":"Sebastien","family":"Pillement","sequence":"additional","affiliation":[{"name":"IRISA, Universit\u00e9 de Rennes, 6 rue de Kerampont, BP 80518, 22302 Lannion, France"}]},{"given":"Daniel","family":"Chillet","sequence":"additional","affiliation":[{"name":"IRISA, Universit\u00e9 de Rennes, 6 rue de Kerampont, BP 80518, 22302 Lannion, France"}]},{"given":"Didier","family":"Demigny","sequence":"additional","affiliation":[{"name":"IRISA, Universit\u00e9 de Rennes, 6 rue de Kerampont, BP 80518, 22302 Lannion, France"}]}],"member":"98","reference":[{"key":"9","first-page":"157","volume-title":"Dynamic and partial reconfiguration in FPGA SoCs: requirements tools and a case study","year":"2005"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.888404"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1007\/b99787"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/4.826825"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2004.03.003"},{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.109"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2007.07.006"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.134"},{"issue":"1","key":"25","first-page":"71","volume":"38","year":"2006","journal-title":"ACM Computing Surveys"},{"key":"26","volume-title":"Appendix E: interconnection networks","year":"2006"}],"container-title":["International Journal of Reconfigurable Computing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/journals\/ijrc\/2010\/390545.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/ijrc\/2010\/390545.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/ijrc\/2010\/390545.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,8,11]],"date-time":"2016-08-11T14:59:01Z","timestamp":1470927541000},"score":1,"resource":{"primary":{"URL":"http:\/\/www.hindawi.com\/journals\/ijrc\/2010\/390545\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010]]},"references-count":11,"alternative-id":["390545","390545"],"URL":"http:\/\/dx.doi.org\/10.1155\/2010\/390545","relation":{},"ISSN":["1687-7195","1687-7209"],"issn-type":[{"value":"1687-7195","type":"print"},{"value":"1687-7209","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010]]}}}
