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Such an approach is justified in the era of sub\u201045\u2009nm technology where an increasingly dominating leakage power component is forcing designers to make the best possible use of on\u2010chip resources. In this paper we present an analysis of two commonly used window\u2010based operations (sum of absolute differences and mean squared error) across a variety of search patterns and block sizes (2 \u00d7 3, 5 \u00d7 5, etc.). We propose a context adaptable architecture that has (i) configurable 2D systolic array and (ii) 2D Configurable Register Array (CRA). CRA can cater to variable pixel access patterns while reusing fetched pixels across search windows. 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