{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,6,10]],"date-time":"2024-06-10T14:34:13Z","timestamp":1718030053095},"reference-count":5,"publisher":"Hindawi Limited","license":[{"start":{"date-parts":[[2007,11,15]],"date-time":"2007-11-15T00:00:00Z","timestamp":1195084800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["60236020"],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2007,11,15]]},"abstract":"This paper describes a novel video specific instruction set architecture for ASIP design. With single \ninstruction multiple data (SIMD) instructions, two destination modes, and video specific\n instructions, an instruction set architecture is introduced to enhance the performance for video\n applications. Furthermore, we quantify the improvement on H.263 encoding. In this paper, we evaluate \n and compare the performance of VS-ISA, other DSPs (digital signal processors), and conventional SIMD\n media extensions in the context of video coding. Our evaluation results show that VS-ISA improves the \n processor's performance by approximately 5x on H.263 encoding, and VS-ISA outperforms other\n architectures by 1.6x to 8.57x in computing IDCT.<\/jats:p>","DOI":"10.1155\/2007\/58431","type":"journal-article","created":{"date-parts":[[2007,11,21]],"date-time":"2007-11-21T13:40:50Z","timestamp":1195652450000},"page":"1-7","source":"Crossref","is-referenced-by-count":6,"title":["A Video Specific Instruction Set Architecture for ASIP design"],"prefix":"10.1155","volume":"2007","author":[{"given":"Zheng","family":"Shen","sequence":"first","affiliation":[]},{"given":"Hu","family":"He","sequence":"additional","affiliation":[]},{"given":"Yanjun","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Yihe","family":"Sun","sequence":"additional","affiliation":[]}],"member":"98","reference":[{"issue":"6","key":"1","doi-asserted-by":"crossref","first-page":"1203","DOI":"10.1109\/5.687835","volume":"86","year":"1998","journal-title":"Proceedings of the IEEE"},{"issue":"2","key":"2","doi-asserted-by":"crossref","first-page":"60","DOI":"10.1109\/40.848473","volume":"20","year":"2000","journal-title":"IEEE Micro"},{"key":"3","year":"2005"},{"issue":"2","key":"8","doi-asserted-by":"crossref","first-page":"86","DOI":"10.1109\/79.664702","volume":"15","year":"1998","journal-title":"IEEE Signal Processing Magazine"},{"issue":"9","key":"16","doi-asserted-by":"crossref","first-page":"1004","DOI":"10.1109\/TCOM.1977.1093941","volume":"25","year":"1977","journal-title":"IEEE Transactions on Communications"}],"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2007\/058431.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/archive\/2007\/058431.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,12,8]],"date-time":"2020-12-08T20:24:53Z","timestamp":1607459093000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.hindawi.com\/journals\/vlsi\/2007\/058431\/abs\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,11,15]]},"references-count":5,"alternative-id":["058431","58431"],"URL":"http:\/\/dx.doi.org\/10.1155\/2007\/58431","relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"value":"1065-514X","type":"print"},{"value":"1563-5171","type":"electronic"}],"subject":[],"published":{"date-parts":[[2007,11,15]]}}}
