{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T20:06:34Z","timestamp":1730318794694,"version":"3.28.0"},"publisher-location":"New York, NY, USA","reference-count":13,"publisher":"ACM","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[1999,5]]},"DOI":"10.1145\/305138.305178","type":"proceedings-article","created":{"date-parts":[[2003,11,14]],"date-time":"2003-11-14T12:54:41Z","timestamp":1068814481000},"page":"119-126","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":32,"title":["Software trace cache"],"prefix":"10.1145","author":[{"given":"Alex","family":"Ram\u00edrez","sequence":"first","affiliation":[{"name":"Computer Architecture Department, Universitat Polit\u00e8cnica de Catalunya, Jordi Girona 1-3, Module D6, 08034 Barcelona (Spain)"}]},{"given":"Josep-L.","family":"Larriba-Pey","sequence":"additional","affiliation":[{"name":"Computer Architecture Department, Universitat Polit\u00e8cnica de Catalunya, Jordi Girona 1-3, Module D6, 08034 Barcelona (Spain)"}]},{"given":"Carlos","family":"Navarro","sequence":"additional","affiliation":[{"name":"Computer Architecture Department, Universitat Polit\u00e8cnica de Catalunya, Jordi Girona 1-3, Module D6, 08034 Barcelona (Spain)"}]},{"given":"Josep","family":"Torrellas","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana Champaign and Computer Architecture Department, Universitat Polit\u00e8cnica de Catalunya, Jordi Girona 1-3, Module D6, 08034 Barcelona (Spain)"}]},{"given":"Mateo","family":"Valero","sequence":"additional","affiliation":[{"name":"Computer Architecture Department, Universitat Polit\u00e8cnica de Catalunya, Jordi Girona 1-3, Module D6, 08034 Barcelona (Spain)"}]}],"member":"320","published-online":{"date-parts":[[1999,5]]},"reference":[{"key":"e_1_3_2_1_1_2","doi-asserted-by":"publisher","DOI":"10.1109\/12.241594"},{"key":"e_1_3_2_1_2_2","doi-asserted-by":"publisher","DOI":"10.1145\/223982.224444"},{"issue":"7","key":"e_1_3_2_1_3_2","first-page":"478","volume":"30","author":"Fisher J. A.","year":"1981","unstructured":"J. A. Fisher . Trace scheduling: A technique for global microcode compaction, i EEE 2~ansactions on Computers , 30 ( 7 ): 478 - 490 , July 1981 . J. A. Fisher. Trace scheduling: A technique for global microcode compaction, iEEE 2~ansactions on Computers, 30(7):478-490, July 1981.","journal-title":"Computers"},{"key":"e_1_3_2_1_4_2","doi-asserted-by":"publisher","DOI":"10.5555\/266800.266803"},{"key":"e_1_3_2_1_5_2","doi-asserted-by":"publisher","DOI":"10.5555\/266800.266829"},{"key":"e_1_3_2_1_6_2","doi-asserted-by":"publisher","DOI":"10.1145\/258915.258931"},{"key":"e_1_3_2_1_7_2","doi-asserted-by":"publisher","DOI":"10.1145\/74925.74953"},{"volume-title":"Proceedings of the .~th Intl. Conference on High Performance Computer Architecture","year":"1998","author":"Kalaxn~itianos J.","key":"e_1_3_2_1_8_2","unstructured":"J. Kalaxn~itianos and D. R. Kaeli . Temporal-based procedure reordering for improved instruction cache performance . Proceedings of the .~th Intl. Conference on High Performance Computer Architecture , Feb. 1998 . J. Kalaxn~itianos and D. R. Kaeli. Temporal-based procedure reordering for improved instruction cache performance. Proceedings of the .~th Intl. Conference on High Performance Computer Architecture, Feb. 1998."},{"key":"e_1_3_2_1_9_2","doi-asserted-by":"publisher","DOI":"10.1145\/279358.279394"},{"key":"e_1_3_2_1_10_2","doi-asserted-by":"publisher","DOI":"10.1145\/93542.93550"},{"key":"e_1_3_2_1_12_2","doi-asserted-by":"publisher","DOI":"10.5555\/243846.243854"},{"key":"e_1_3_2_1_13_2","first-page":"360","volume-title":"Conferer~ce on High Performance Computer Architecture","author":"Torrellas J.","year":"1995","unstructured":"J. Torrellas , C. Xia , and R. Daigle . Optimizing instruction cache performance for operating system intensive workloads. Proceedit, gs of the 18t Intl . Conferer~ce on High Performance Computer Architecture , pages 360 - 369 , Jan. 1995 . J. Torrellas, C. Xia, and R. Daigle. Optimizing instruction cache performance for operating system intensive workloads. Proceedit, gs of the 18t Intl. Conferer~ce on High Performance Computer Architecture, pages 360- 369, Jan. 1995."},{"key":"e_1_3_2_1_14_2","doi-asserted-by":"publisher","DOI":"10.1145\/165939.165956"}],"event":{"name":"ICS99: The 13th ACM International Conference on Supercomputing","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture"],"location":"Rhodes Greece","acronym":"ICS99"},"container-title":["Proceedings of the 13th international conference on Supercomputing"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/305138.305178","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,6]],"date-time":"2023-01-06T22:07:37Z","timestamp":1673042857000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/305138.305178"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1999,5]]},"references-count":13,"alternative-id":["10.1145\/305138.305178","10.1145\/305138"],"URL":"https:\/\/doi.org\/10.1145\/305138.305178","relation":{},"subject":[],"published":{"date-parts":[[1999,5]]},"assertion":[{"value":"1999-05-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}