{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,7,27]],"date-time":"2024-07-27T04:39:30Z","timestamp":1722055170895},"reference-count":26,"publisher":"Association for Computing Machinery (ACM)","issue":"1","funder":[{"DOI":"10.13039\/501100002855","name":"Ministry of Science and Technology of the People's Republic of China","doi-asserted-by":"publisher","award":["2009AA01170"],"id":[{"id":"10.13039\/501100002855","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2013,1]]},"abstract":"Reliability has become an increasingly important concern for SRAM-based field programmable gate arrays (FPGAs). Targeting SEU (single event upset) in SRAM-based FPGAs, this article first develops an SEU evaluation framework that can quantify the failure sensitivity for each configuration bit during design time. This framework considers detailed fault behavior and logic masking on a post-layout FPGA application and performs logic simulation on various circuit elements for fault evaluation. Applying this framework on MCNC benchmark circuits, we first characterize SEUs with respect to different FPGA circuits and architectures, for example, bidirectional routing and unidirectional routing. We show that in both routing architectures, interconnects not only contribute to the lion's share of the SEU-induced functional failures, but also present higher failure rates per configuration bits than LUTs. Particularly, local interconnect multiplexers in logic blocks have the highest failure rate per configuration bit. Then, we evaluate three recently proposed SEU mitigation algorithms, IPD, IPF, and IPV, which are all logic resynthesis-based with little or no overhead on placement and routing. Different fault mitigating capabilities at the chip level are revealed, and it demonstrates that algorithms with explicit consideration for interconnect significantly mitigate the SEU at the chip level, for example, IPV achieves 61% failure rate reduction on average against IPF with about 15%. In addition, the combination of the three algorithms delivers over 70% failure rate reduction on average at the chip level. The experiments also reveal that in order to improve fault tolerance at the chip level, it is necessary for future fault mitigation algorithms to concern not only LUT or interconnect faults, but also their interactions. We envision that our framework can be used to cast more useful insights for more robust FPGA circuits, architectures, and better synthesis algorithms.<\/jats:p>","DOI":"10.1145\/2390191.2390204","type":"journal-article","created":{"date-parts":[[2013,1,15]],"date-time":"2013-01-15T15:32:11Z","timestamp":1358263931000},"page":"1-18","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":14,"title":["SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms"],"prefix":"10.1145","volume":"18","author":[{"given":"Naifeng","family":"Jing","sequence":"first","affiliation":[{"name":"Shanghai Jiao Tong University"}]},{"given":"Ju-Yueh","family":"Lee","sequence":"additional","affiliation":[{"name":"University of California, Los Angeles"}]},{"given":"Zhe","family":"Feng","sequence":"additional","affiliation":[{"name":"University of California, Los Angeles"}]},{"given":"Weifeng","family":"He","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University"}]},{"given":"Zhigang","family":"Mao","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University"}]},{"given":"Lei","family":"He","sequence":"additional","affiliation":[{"name":"University of California, Los Angeles"}]}],"member":"320","published-online":{"date-parts":[[2013,1,16]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046212"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2007.910426"},{"key":"e_1_2_1_3_1","volume-title":"Proceedings of the Conference on Design, Automation and Test in Europe. 584--589","author":"Bellato M.","unstructured":"Bellato , M. , Bernardi , P. , Bortolato , D. , Candelori , A. , Ceschia , M. , Paccagnella , A. , Rebaudengo , M. , Sonza Reorda , M. , Violante , M. , and Zambolin , P . 2004. Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA . In Proceedings of the Conference on Design, Automation and Test in Europe. 584--589 . Bellato, M., Bernardi, P., Bortolato, D., Candelori, A., Ceschia, M., Paccagnella, A., Rebaudengo, M., Sonza Reorda, M., Violante, M., and Zambolin, P. 2004. Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA. In Proceedings of the Conference on Design, Automation and Test in Europe. 584--589."},{"key":"e_1_2_1_4_1","volume-title":"Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications. 213--222","author":"Betz V.","unstructured":"Betz , V. , and Rose , J . 1997. VPR: A new packing, placement and routing tool for FPGA research . In Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications. 213--222 . Betz, V., and Rose, J. 1997. VPR: A new packing, placement and routing tool for FPGA research. In Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications. 213--222."},{"key":"e_1_2_1_5_1","unstructured":"Chapman K. 2010. SEU strategies for Virtex-5 devices. Chapman K. 2010. SEU strategies for Virtex-5 devices."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687422"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2011.95"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2005.120"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278564"},{"key":"e_1_2_1_10_1","volume-title":"Proceedings of the International Conference on Military and Aerospace Programmable Logic Devices.","author":"Graham P.","unstructured":"Graham , P. , Caffrey , M. , Zimmerman , J. , Sundararajan , P. , Johnson , E. , and Patterson , C . 2003. Consequences and categories of SRAM FPGA configuration SEUs . In Proceedings of the International Conference on Military and Aerospace Programmable Logic Devices. Graham, P., Caffrey, M., Zimmerman, J., Sundararajan, P., Johnson, E., and Patterson, C. 2003. Consequences and categories of SRAM FPGA configuration SEUs. In Proceedings of the International Conference on Military and Aerospace Programmable Logic Devices."},{"key":"e_1_2_1_11_1","volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications.","author":"H\u00e9ron O.","unstructured":"H\u00e9ron , O. , Arnaout , T. , and Wunderlich , H . -j. 2005. On the reliability evaluation of SRAM-based FPGA designs . In Proceedings of the International Conference on Field Programmable Logic and Applications. H\u00e9ron, O., Arnaout, T., and Wunderlich, H.-j. 2005. On the reliability evaluation of SRAM-based FPGA designs. In Proceedings of the International Conference on Field Programmable Logic and Applications."},{"key":"e_1_2_1_12_1","volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design. 706--713","author":"Hu Y.","unstructured":"Hu , Y. , Feng , Z. , He , L. , and Majumdar , R . 2008. Robust FPGA resynthesis based on fault-tolerant boolean matching . In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design. 706--713 . Hu, Y., Feng, Z., He, L., and Majumdar, R. 2008. Robust FPGA resynthesis based on fault-tolerant boolean matching. In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design. 706--713."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2011.57"},{"key":"e_1_2_1_14_1","volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design. 582--586","author":"Jing N.","unstructured":"Jing , N. , Lee , J.-Y. , He , W. , Mao , Z. , and He , L . 2011b. Mitigating FPGA interconnect soft errors by in-place LUT inversion . In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design. 582--586 . Jing, N., Lee, J.-Y., He, W., Mao, Z., and He, L. 2011b. Mitigating FPGA interconnect soft errors by in-place LUT inversion. In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design. 582--586."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2003.821791"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837391"},{"key":"e_1_2_1_17_1","volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design. 149--154","author":"Krishnaswamy S.","unstructured":"Krishnaswamy , S. , Plaza , S. M. , Markov , I. L. , and Hayes , J. P . 2007. Enhancing design robustness with reliability-aware resynthesis and logic simulation . In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design. 149--154 . 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