{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,15]],"date-time":"2024-09-15T22:30:14Z","timestamp":1726439414470},"reference-count":26,"publisher":"Association for Computing Machinery (ACM)","issue":"4","funder":[{"name":"Engineering Research Center program","award":["2011-0000975"]},{"DOI":"10.13039\/501100004085","name":"Ministry of Education, Science and Technology","doi-asserted-by":"publisher","award":["2010-0011534"],"id":[{"id":"10.13039\/501100004085","id-type":"DOI","asserted-by":"publisher"}]},{"name":"NRL Program","award":["2010-0018465"]},{"DOI":"10.13039\/100000143","name":"Division of Computing and Communication Foundations","doi-asserted-by":"publisher","award":["CCF-0916652CCF-1055094 (CAREER)"],"id":[{"id":"10.13039\/100000143","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000151","name":"Division of Industrial Innovation and Partnerships","doi-asserted-by":"publisher","award":["IIP-0856090"],"id":[{"id":"10.13039\/100000151","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2011,10]]},"abstract":"Coarse-grained reconfigurable architectures (CGRAs) promise high performance at high power efficiency. They fulfil this promise by keeping the hardware extremely simple, and moving the complexity to application mapping. One major challenge comes in the form of data mapping. For reasons of power-efficiency and complexity, CGRAs use multibank local memory, and a row of PEs share memory access. In order for each row of the PEs to access any memory bank, there is a hardware arbiter between the memory requests generated by the PEs and the banks of the local memory. However, a fundamental restriction remains in that a bank cannot be accessed by two different PEs at the same time. We propose to meet this challenge by mapping application operations onto PEs and data into memory banks in a way that avoids such conflicts. To further improve performance on multibank memories, we propose a compiler optimization for CGRA mapping to reduce the number of memory operations by exploiting data reuse. Our experimental results on kernels from multimedia benchmarks demonstrate that our local memory-aware compilation approach can generate mappings that are up to 53% better in performance (26% on average) compared to a memory-unaware scheduler.<\/jats:p>","DOI":"10.1145\/2003695.2003702","type":"journal-article","created":{"date-parts":[[2011,10,25]],"date-time":"2011-10-25T12:23:05Z","timestamp":1319545385000},"page":"1-27","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":13,"title":["Memory access optimization in compilation for coarse-grained reconfigurable architectures"],"prefix":"10.1145","volume":"16","author":[{"given":"Yongjoo","family":"Kim","sequence":"first","affiliation":[{"name":"Seoul National University, Seoul, Korea"}]},{"given":"Jongeun","family":"Lee","sequence":"additional","affiliation":[{"name":"Ulsan National Institute of Science and Technology, Ulsan, Korea"}]},{"given":"Aviral","family":"Shrivastava","sequence":"additional","affiliation":[{"name":"Arizona State University"}]},{"given":"Yunheung","family":"Paek","sequence":"additional","affiliation":[{"name":"Seoul National University, Seoul, Korea"}]}],"member":"320","published-online":{"date-parts":[[2011,10,27]]},"reference":[{"volume-title":"Proceedings of the Conference on Design, Automation and Test in Europe (DATE'06)","author":"Ahn M.","key":"e_1_2_1_1_1"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.49"},{"key":"e_1_2_1_3_1","unstructured":"Bouwens F. 2006. Power and performance optimization for Adres. M.S. dissertation Delft University of Technology. Bouwens F. 2006. Power and performance optimization for Adres. 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