{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T19:11:04Z","timestamp":1730315464443,"version":"3.28.0"},"publisher-location":"New York, NY, USA","reference-count":46,"publisher":"ACM","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2011,6,4]]},"DOI":"10.1145\/2000064.2000115","type":"proceedings-article","created":{"date-parts":[[2011,6,28]],"date-time":"2011-06-28T17:34:50Z","timestamp":1309282490000},"page":"425-436","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":38,"title":["Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems"],"prefix":"10.1145","author":[{"given":"Aniruddha N.","family":"Udipi","sequence":"first","affiliation":[{"name":"University of Utah, Salt Lake City, UT, USA"}]},{"given":"Naveen","family":"Muralimanohar","sequence":"additional","affiliation":[{"name":"Hewlett Packard, Palo Alto, CA, USA"}]},{"given":"Rajeev","family":"Balasubramonian","sequence":"additional","affiliation":[{"name":"University of Utah, Salt Lake City, UT, USA"}]},{"given":"Al","family":"Davis","sequence":"additional","affiliation":[{"name":"University of Utah, Salt Lake City, UT, USA"}]},{"given":"Norman P.","family":"Jouppi","sequence":"additional","affiliation":[{"name":"Hewlett Packard, Palo Alto, CA, USA"}]}],"member":"320","published-online":{"date-parts":[[2011,6,4]]},"reference":[{"key":"e_1_3_2_2_1_1","unstructured":"CACTI\n : An Integrated Cache and Memory Access Time Cycle Time Area Leakage and Dynamic Power Model. http:\/\/www.hpl.hp.com\/research\/cacti\/. CACTI: An Integrated Cache and Memory Access Time Cycle Time Area Leakage and Dynamic Power Model. http:\/\/www.hpl.hp.com\/research\/cacti\/."},{"key":"e_1_3_2_2_2_1","unstructured":"Fully-Buffered DIMM Technology in HP ProLiant Servers - Technology Brief. http:\/\/www.hp.com. Fully-Buffered DIMM Technology in HP ProLiant Servers - Technology Brief. http:\/\/www.hp.com."},{"key":"e_1_3_2_2_3_1","unstructured":"STREAM - Sustainable Memory Bandwidth in High Performance Computers. http:\/\/www.cs.virginia.edu\/stream\/. STREAM - Sustainable Memory Bandwidth in High Performance Computers. http:\/\/www.cs.virginia.edu\/stream\/."},{"key":"e_1_3_2_2_4_1","unstructured":"Virtutech Simics Full System Simulator. http:\/\/www.virtutech.com. Virtutech Simics Full System Simulator. http:\/\/www.virtutech.com."},{"key":"e_1_3_2_2_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2008.4658649"},{"volume-title":"Report of the NSF Blue-Ribbon Advisory Panel on Cyberinfrastructure. Technical report","year":"2003","author":"Atkins D. E.","key":"e_1_3_2_2_6_1","unstructured":"D. E. Atkins Report of the NSF Blue-Ribbon Advisory Panel on Cyberinfrastructure. Technical report , National Science Foundation , 2003 . D. E. Atkins et al. Report of the NSF Blue-Ribbon Advisory Panel on Cyberinfrastructure. Technical report, National Science Foundation, 2003."},{"volume-title":"Non-Volatile Memories Workshop","year":"2011","author":"Awasthi M.","key":"e_1_3_2_2_7_1","unstructured":"M. Awasthi Handling PCM Resistance Drift with Device, Circuit, Architecture, and System Solutions . In Non-Volatile Memories Workshop , 2011 . M. Awasthi et al. Handling PCM Resistance Drift with Device, Circuit, Architecture, and System Solutions. In Non-Volatile Memories Workshop, 2011."},{"key":"e_1_3_2_2_8_1","doi-asserted-by":"publisher","DOI":"10.1364\/AO.47.003500"},{"key":"e_1_3_2_2_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/1643608"},{"key":"e_1_3_2_2_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815978"},{"key":"e_1_3_2_2_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2007.911057"},{"volume-title":"The PARSEC Benchmark Suite: Characterization and Architectural Implications. Technical report","year":"2008","author":"Benia C.","key":"e_1_3_2_2_12_1","unstructured":"C. Benia The PARSEC Benchmark Suite: Characterization and Architectural Implications. Technical report , Princeton University , 2008 . C. Benia et al. The PARSEC Benchmark Suite: Characterization and Architectural Implications. Technical report, Princeton University, 2008."},{"key":"e_1_3_2_2_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.18"},{"key":"e_1_3_2_2_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555809"},{"key":"e_1_3_2_2_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629575.1629589"},{"key":"e_1_3_2_2_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.43"},{"key":"e_1_3_2_2_17_1","volume-title":"Principles and Practices of Interconnection Networks. Morgan Kaufmann","author":"Dally W.","year":"2003","unstructured":"W. Dally and B. Towles . Principles and Practices of Interconnection Networks. Morgan Kaufmann , 1 st edition, 2003 . W. Dally and B. Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann, 1st edition, 2003.","edition":"1"},{"key":"e_1_3_2_2_18_1","unstructured":"Elpida Memory Inc. News Release: Elpida Completes Development of Cu-TSV (Through Silicon Via) Multi-Layer 8-Gigabit DRAM. http:\/\/www.elpida.com\/pdfs\/pr\/2009-08-27e.pdf. Elpida Memory Inc. News Release: Elpida Completes Development of Cu-TSV (Through Silicon Via) Multi-Layer 8-Gigabit DRAM. http:\/\/www.elpida.com\/pdfs\/pr\/2009-08-27e.pdf."},{"volume-title":"Optics Express","year":"2007","author":"Fang K.","key":"e_1_3_2_2_19_1","unstructured":"K. Fang Mode-locked Silicon Evanescent Lasers . Optics Express , September 2007 . K. Fang et al. Mode-locked Silicon Evanescent Lasers. Optics Express, September 2007."},{"key":"e_1_3_2_2_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTI.2008.25"},{"key":"e_1_3_2_2_22_1","unstructured":"ITRS. International Technology Roadmap for Semiconductors 2008 Update. ITRS. International Technology Roadmap for Semiconductors 2008 Update."},{"key":"e_1_3_2_2_23_1","first-page":"95","author":"Ahn J.","year":"2009","unstructured":"J. Ahn Applied Physics A: Materials Science and Processing , 95 , 2009 . J. Ahn et al. Devices and architectures for photonic chip-scale integration. Applied Physics A: Materials Science and Processing, 95, 2009.","journal-title":"Applied Physics A: Materials Science and Processing"},{"volume-title":"DRAM, Disk","year":"2008","author":"Jacob B.","key":"e_1_3_2_2_24_1","unstructured":"B. Jacob , S. W. Ng , and D. T. Wang . Memory Systems - Cache , DRAM, Disk . Elsevier , 2008 . B. Jacob, S. W. Ng, and D. T. Wang. Memory Systems - Cache, DRAM, Disk. Elsevier, 2008."},{"volume-title":"IBM Power Aware Systems. Personal Correspondence","year":"2011","key":"e_1_3_2_2_25_1","unstructured":"John Carter , IBM Power Aware Systems. Personal Correspondence , 2011 . John Carter, IBM Power Aware Systems. Personal Correspondence, 2011."},{"volume-title":"DDR DRAM Using Through-Silicon-Via Technology. In Proceedings of ISSCC","year":"2009","author":"Kang U.","key":"e_1_3_2_2_26_1","unstructured":"U. Kang DDR DRAM Using Through-Silicon-Via Technology. In Proceedings of ISSCC , 2009 . U. Kang et al. 8Gb 3D DDR DRAM Using Through-Silicon-Via Technology. In Proceedings of ISSCC, 2009."},{"key":"e_1_3_2_2_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.28"},{"key":"e_1_3_2_2_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736024"},{"volume-title":"ExaScale Computing Study: Technology Challenges in Achieving Exascale Systems","year":"2008","author":"P.","key":"e_1_3_2_2_29_1","unstructured":"P. Kogge(Editor). ExaScale Computing Study: Technology Challenges in Achieving Exascale Systems . Defense Advanced Research Projects Agency (DARPA) , 2008 . P. Kogge(Editor). ExaScale Computing Study: Technology Challenges in Achieving Exascale Systems. Defense Advanced Research Projects Agency (DARPA), 2008."},{"key":"e_1_3_2_2_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"e_1_3_2_2_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555789"},{"key":"e_1_3_2_2_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.15"},{"key":"e_1_3_2_2_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508269"},{"key":"e_1_3_2_2_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2014298"},{"key":"e_1_3_2_2_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/1054943.1054954"},{"key":"e_1_3_2_2_36_1","doi-asserted-by":"publisher","DOI":"10.5555\/2014698.2014901"},{"volume-title":"Coding for Limiting Current in Memristor Crossbar Memories. In Non-Volatile Memories Workshop","year":"2011","author":"Ordentlich E.","key":"e_1_3_2_2_37_1","unstructured":"E. Ordentlich Coding for Limiting Current in Memristor Crossbar Memories. In Non-Volatile Memories Workshop , 2011 . E. Ordentlich et al. Coding for Limiting Current in Memristor Crossbar Memories. In Non-Volatile Memories Workshop, 2011."},{"key":"e_1_3_2_2_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555760"},{"key":"e_1_3_2_2_39_1","unstructured":"Raymond G. Beausoleil HP Labs. Personal Correspondence 2010. Raymond G. Beausoleil HP Labs. Personal Correspondence 2010."},{"key":"e_1_3_2_2_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859620"},{"volume-title":"Digital Optics. Proceedings of IEEE","year":"1989","author":"Streibl N.","key":"e_1_3_2_2_41_1","unstructured":"N. Streibl Digital Optics. Proceedings of IEEE , 1989 . N. Streibl et al. Digital Optics. Proceedings of IEEE, 1989."},{"key":"e_1_3_2_2_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2009.341"},{"key":"e_1_3_2_2_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815983"},{"key":"e_1_3_2_2_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.35"},{"volume-title":"High-Density TSV Bandwidth. In Proceedings of HPCA","year":"2010","author":"Woo D. H.","key":"e_1_3_2_2_45_1","unstructured":"D. H. Woo An Optimized 3D-Stacked Memory Architecture by Exploiting Excessive , High-Density TSV Bandwidth. In Proceedings of HPCA , 2010 . D. H. Woo et al. An Optimized 3D-Stacked Memory Architecture by Exploiting Excessive, High-Density TSV Bandwidth. In Proceedings of HPCA, 2010."},{"key":"e_1_3_2_2_46_1","first-page":"325","volume":"435","author":"Xu Q.","year":"2005","unstructured":"Q. Xu Micrometre-Scale Silicon Electro-Optic Modulator. Nature , 435 : 325 -- 327 , May 2005 . Q. Xu et al. Micrometre-Scale Silicon Electro-Optic Modulator. Nature, 435:325--327, May 2005.","journal-title":"Micrometre-Scale Silicon Electro-Optic Modulator. Nature"},{"key":"e_1_3_2_2_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815975"}],"event":{"name":"ISCA '11: The 38th Annual International Symposium on Computer Architecture","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture","IEEE CS"],"location":"San Jose California USA","acronym":"ISCA '11"},"container-title":["Proceedings of the 38th annual international symposium on Computer architecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2000064.2000115","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,4]],"date-time":"2023-09-04T20:40:03Z","timestamp":1693860003000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2000064.2000115"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,6,4]]},"references-count":46,"alternative-id":["10.1145\/2000064.2000115","10.1145\/2000064"],"URL":"http:\/\/dx.doi.org\/10.1145\/2000064.2000115","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/2024723.2000115","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2011,6,4]]},"assertion":[{"value":"2011-06-04","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}
