{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T23:49:28Z","timestamp":1725666568789},"publisher-location":"New York, NY, USA","reference-count":28,"publisher":"ACM","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2009,12,12]]},"DOI":"10.1145\/1645213.1645222","type":"proceedings-article","created":{"date-parts":[[2009,12,15]],"date-time":"2009-12-15T07:55:59Z","timestamp":1260863759000},"page":"31-36","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":12,"title":["Architecture design principles for the integration of synchronization interfaces into Network-on-Chip switches"],"prefix":"10.1145","author":[{"given":"Daniele","family":"Ludovici","sequence":"first","affiliation":[{"name":"Computer Engineering Lab., TUDelft, Delft, The Netherlands"}]},{"given":"Alessandro","family":"Strano","sequence":"additional","affiliation":[{"name":"University of Ferrara, Ferrara, Italy"}]},{"given":"Davide","family":"Bertozzi","sequence":"additional","affiliation":[{"name":"University of Ferrara, Ferrara, Italy"}]}],"member":"320","published-online":{"date-parts":[[2009,12,12]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2009.5071471"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.831476"},{"key":"e_1_3_2_1_3_1","first-page":"2002","article-title":"Simulation and Synthesis Techniques for Asynchronous FIFO Design withAsynchronous Pointer Comparison","author":"Cummings C.","year":"2002","unstructured":"C. Cummings , P. Alfke , \" Simulation and Synthesis Techniques for Asynchronous FIFO Design withAsynchronous Pointer Comparison \", SNUG- 2002 , San Jos\u00e8, CA, 2002 . C. Cummings, P. Alfke, \"Simulation and Synthesis Techniques for Asynchronous FIFO Design withAsynchronous Pointer Comparison\", SNUG-2002, San Jos\u00e8, CA, 2002.","journal-title":"SNUG-"},{"volume-title":"Cambridge University Press","year":"1998","author":"Dally W. J.","key":"e_1_3_2_1_4_1","unstructured":"W. J. Dally , J. W. Poulton , \" Digital Systems Engineering\" , Cambridge University Press , 1998 W. J. Dally, J. W. Poulton, \"Digital Systems Engineering\", Cambridge University Press, 1998"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996586"},{"key":"e_1_3_2_1_6_1","first-page":"1765","volume-title":"IEEE Conf. Solid-State Circuits","author":"Caput P.","year":"2006","unstructured":"P. Caput , C. Svensson , \" An On-Chip Delay- and Skew-Inscnsitive Multicycle Communication Scheme\" , IEEE Conf. Solid-State Circuits , pp. 1765 -- 1774 , 2006 . P. Caput, C. Svensson, \"An On-Chip Delay- and Skew-Inscnsitive Multicycle Communication Scheme\", IEEE Conf. Solid-State Circuits, pp. 1765--1774, 2006."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2007.14"},{"key":"e_1_3_2_1_8_1","first-page":"122","article-title":"Self-Timed Mesochronous Interconnections for High-Speed VLSI Systems","author":"Kim S.","year":"1996","unstructured":"S. Kim , R. Sridhar , \" Self-Timed Mesochronous Interconnections for High-Speed VLSI Systems \", GLSVLSI , pp. 122 -- 128 , 1996 . S. Kim, R. Sridhar, \"Self-Timed Mesochronous Interconnections for High-Speed VLSI Systems\", GLSVLSI, pp. 122--128, 1996.","journal-title":"GLSVLSI"},{"key":"e_1_3_2_1_9_1","first-page":"3","article-title":"Implementing a STARI chip","author":"Greenstreet M. R.","year":"1995","unstructured":"M. R. Greenstreet , \" Implementing a STARI chip \", ICCD , pp. 3 , 1995 . M. R. Greenstreet, \"Implementing a STARI chip\", ICCD, pp. 3, 1995.","journal-title":"ICCD"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/82.917781"},{"key":"e_1_3_2_1_11_1","first-page":"605","article-title":"A New Mesochronous Clocking Scheme for Synchronization in SoC","author":"Mesgarzadeh B.","year":"2002","unstructured":"B. Mesgarzadeh , C. Svensson , A. Alvandpour , \" A New Mesochronous Clocking Scheme for Synchronization in SoC \", ISCAS , pp. 605 -- 609 , 2002 . B. Mesgarzadeh, C. Svensson, A. Alvandpour, \"A New Mesochronous Clocking Scheme for Synchronization in SoC\", ISCAS, pp. 605--609, 2002.","journal-title":"ISCAS"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.5555\/785169.785384"},{"volume-title":"Proc. Swedish System-on-Chip Conf.","year":"2003","author":"Wiklund D.","key":"e_1_3_2_1_13_1","unstructured":"D. Wiklund , \" Mesochronous Clocking and Communication in On-Chip Networks\" , Proc. Swedish System-on-Chip Conf. , 2003 . D. Wiklund, \"Mesochronous Clocking and Communication in On-Chip Networks\", Proc. Swedish System-on-Chip Conf., 2003."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2007.40"},{"volume-title":"VLSI Design","year":"2007","author":"Ghoneima M.","key":"e_1_3_2_1_15_1","unstructured":"M. Ghoneima , Y. Ismail , M. Khellah , V. De , \" Variation-Tolerant and Low-Power Source-Synchronous Multi- Cycle On-Chip Interconnection Scheme\" , VLSI Design , 2007 . M. Ghoneima, Y. Ismail, M. Khellah, V. De, \"Variation-Tolerant and Low-Power Source-Synchronous Multi-Cycle On-Chip Interconnection Scheme\", VLSI Design, 2007."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1531542.1531574"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.48"},{"key":"e_1_3_2_1_18_1","first-page":"1","volume-title":"Int. Conf. on Nano-Networks","author":"Mangano D.","year":"2006","unstructured":"D. Mangano , R. Locatelli , A. Scandurra , C. Pistritto , M. Coppola , L. Fanucci , F. Vitullo , D. Zandri , \" Skew Insensitive Physical Links for Networks-on-Chip\" , Int. Conf. on Nano-Networks , pp. 1 -- 5 , 2006 . D. Mangano, R. Locatelli, A. Scandurra, C. Pistritto, M. Coppola, L. Fanucci, F. Vitullo, D. Zandri, \"Skew Insensitive Physical Links for Networks-on-Chip\", Int. Conf. on Nano-Networks, pp. 1--5, 2006."},{"volume-title":"VLSI Design","year":"2007","author":"Loi I.","key":"e_1_3_2_1_19_1","unstructured":"I. Loi , F. Angiolini , L. Benini , \" Developing Mesochronous Synchronizers to Enable 3D NoCs\" , VLSI Design , 2007 . I. Loi, F. Angiolini, L. Benini, \"Developing Mesochronous Synchronizers to Enable 3D NoCs\", VLSI Design, 2007."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2009.5071473"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.1"},{"volume-title":"October","year":"1984","author":"Chapiro D. M.","key":"e_1_3_2_1_22_1","unstructured":"D. M. Chapiro , \" Globally-Asynchronous Locally-Synchronous Systems\". Ph D Dissertation , Stanford University , October 1984 . D. M. Chapiro, \"Globally-Asynchronous Locally-Synchronous Systems\". PhD Dissertation, Stanford University, October 1984."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2001947"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.881217"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373392"},{"key":"e_1_3_2_1_27_1","first-page":"428","volume-title":"Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC)","author":"Yu Z.","year":"2006","unstructured":"Z. Yu , M. Meeuwsen , R. Apperson , O. Sattari , M. Lai , J. Webb , E. Work , T. Mohsenin , M. Singh , and B. Baas , \" An asynchronous array of simple processors for DSP applications \". in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC) , Feb. 2006 , pp. 428 -- 429 . Z. Yu, M. Meeuwsen, R. Apperson, O. Sattari, M. Lai, J. Webb, E. Work, T. Mohsenin, M. Singh, and B. Baas, \"An asynchronous array of simple processors for DSP applications\". in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), Feb. 2006, pp. 428--429."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1081081.1081138"}],"event":{"name":"Micro-42: The 42nd Annual IEEE\/ACM International Symposium on Microarchitecture","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","IEEE-CS TG u-Arch"],"location":"New York New York","acronym":"Micro-42"},"container-title":["Proceedings of the 2nd International Workshop on Network on Chip Architectures"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1645213.1645222","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,10]],"date-time":"2023-01-10T23:25:50Z","timestamp":1673393150000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1645213.1645222"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,12,12]]},"references-count":28,"alternative-id":["10.1145\/1645213.1645222","10.1145\/1645213"],"URL":"https:\/\/doi.org\/10.1145\/1645213.1645222","relation":{},"subject":[],"published":{"date-parts":[[2009,12,12]]},"assertion":[{"value":"2009-12-12","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}