{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,3,3]],"date-time":"2024-03-03T08:52:46Z","timestamp":1709455966913},"reference-count":36,"publisher":"Association for Computing Machinery (ACM)","issue":"4","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2008,1]]},"abstract":"\n Level-one caches normally reside on a processor's critical path, which determines clock frequency. Therefore, fast access to level-one cache is important. Direct-mapped caches exhibit faster access time, but poor hit rates, compared with same sized set-associative caches because of nonuniform accesses to the cache sets. The nonuniform accesses generate more cache misses in some sets, while other sets are underutilized. We propose to increase the decoder length and, hence, reduce the accesses to heavily used sets without dynamically detecting the cache set usage information. We increase the access to the underutilized cache sets by incorporating a replacement policy into the cache design using programmable decoders. On average, the proposed techniques achieve as low a miss rate as a traditional 4-way cache on all 26 SPEC2K benchmarks for the instruction and data caches, respectively. This translates into an average IPC improvement of 21.5 and 42.4% for SPEC2K integer and floating-point benchmarks, respectively. The\n B-Cache<\/jats:italic>\n consumes 10.5% more power per access, but exhibits a 12% total memory access-related energy savings as a result of the miss rate reductions, and, hence, the reduction to applications' execution time. Compared with previous techniques that aim at reducing the miss rate of direct-mapped caches, our technique requires only one cycle to access all cache hits and has the same access time of a direct-mapped cache.\n <\/jats:p>","DOI":"10.1145\/1328195.1328200","type":"journal-article","created":{"date-parts":[[2008,2,8]],"date-time":"2008-02-08T15:32:16Z","timestamp":1202484736000},"page":"1-31","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Reducing cache misses through programmable decoders"],"prefix":"10.1145","volume":"4","author":[{"given":"Chuanjun","family":"Zhang","sequence":"first","affiliation":[{"name":"University of Missouri-Kansas City, Kansas City, Missouri"}]}],"member":"320","published-online":{"date-parts":[[2008,1,30]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165153"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339691"},{"key":"e_1_2_1_3_1","volume-title":"Proceedings of Design, Automation, and Test in Europe Conference and Exhibition.","author":"Agarwal A."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/195473.195527"},{"key":"e_1_2_1_5_1","doi-asserted-by":"crossref","unstructured":"Burger D. and Austin T. M. 1997. The SimpleScalar Tool Set Version 2.0. Univ. of Wisconsin-Madison Computer Sciences Dept. Technical Report #1342 June. Burger D. and Austin T. M. 1997. The SimpleScalar Tool Set Version 2.0. Univ. of Wisconsin-Madison Computer Sciences Dept. Technical Report #1342 June.","DOI":"10.1145\/268806.268810"},{"key":"e_1_2_1_6_1","unstructured":"Cadence Corporation. http:\/\/www.cadence.com Cadence Corporation. http:\/\/www.cadence.com"},{"key":"e_1_2_1_7_1","volume-title":"Proceedings of the High Performance Computer Architecture. 244--253","author":"Calder B."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/278677.278689"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/359619.359634"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/566408.566445"},{"key":"e_1_2_1_11_1","volume-title":"Proceedings of the International Symposium on Computer Architecture.","author":"Flautner K."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313860"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/775832.776052"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/325164.325162"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/232973.232986"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379268"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2004.10015"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/74925.74941"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/192724.192742"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803943"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/237090.237202"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/291069.291053"},{"key":"e_1_2_1_23_1","unstructured":"Reinmann G. and Jouppi N. P. 1999. CACTI2.0: An Integrated Cache Timing and Power Model. COMPAQ Western Research Lab. Reinmann G. and Jouppi N. P. 1999. CACTI2.0: An Integrated Cache Timing and Power Model. COMPAQ Western Research Lab."},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.726584"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165152"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605403"},{"key":"e_1_2_1_27_1","unstructured":"Standard Performance Evaluation Corporation. http:\/\/www.specbench.org\/osg\/cpu2000\/. Standard Performance Evaluation Corporation. http:\/\/www.specbench.org\/osg\/cpu2000\/."},{"key":"e_1_2_1_28_1","unstructured":"Sun Microsystems Inc. 2006. http:\/\/www.sun.com\/servers\/entry\/v210\/datasheet.pdf. Sun Microsystems Inc. 2006. http:\/\/www.sun.com\/servers\/entry\/v210\/datasheet.pdf."},{"key":"e_1_2_1_29_1","volume-title":"C. T. Pre-compiled SPEC2000 Alpha Binaries. Available at: http:\/\/www.simplescalar.org.","author":"Weaver"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/218864.218865"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/216585.216588"},{"key":"e_1_2_1_32_1","doi-asserted-by":"crossref","unstructured":"Yoshimoto M. et al. 1983. A divided word-line structure in the static RAM and its application to a 64k full CMOS RAM. IEEE J. Solid-State Circuits SC-21 479--485. Yoshimoto M. et al. 1983. A divided word-line structure in the static RAM and its application to a 64k full CMOS RAM. IEEE J. Solid-State Circuits SC-21 479--485.","DOI":"10.1109\/JSSC.1983.1051981"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.12"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859635"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/1061267.1061270"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.621212"}],"container-title":["ACM Transactions on Architecture and Code Optimization"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1328195.1328200","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,12,28]],"date-time":"2022-12-28T18:46:38Z","timestamp":1672253198000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1328195.1328200"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,1]]},"references-count":36,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2008,1]]}},"alternative-id":["10.1145\/1328195.1328200"],"URL":"https:\/\/doi.org\/10.1145\/1328195.1328200","relation":{},"ISSN":["1544-3566","1544-3973"],"issn-type":[{"value":"1544-3566","type":"print"},{"value":"1544-3973","type":"electronic"}],"subject":[],"published":{"date-parts":[[2008,1]]},"assertion":[{"value":"2006-08-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2007-05-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2008-01-30","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}
