{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T01:29:25Z","timestamp":1725672565438},"publisher-location":"New York, NY, USA","reference-count":26,"publisher":"ACM","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2005,6,20]]},"DOI":"10.1145\/1088149.1088176","type":"proceedings-article","created":{"date-parts":[[2005,11,7]],"date-time":"2005-11-07T17:34:39Z","timestamp":1131384879000},"page":"199-208","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":14,"title":["TAPE"],"prefix":"10.1145","author":[{"given":"Hassan","family":"Chafi","sequence":"first","affiliation":[{"name":"Stanford University"}]},{"given":"Chi Cao","family":"Minh","sequence":"additional","affiliation":[{"name":"Stanford University"}]},{"given":"Austen","family":"McDonald","sequence":"additional","affiliation":[{"name":"Stanford University"}]},{"given":"Brian D.","family":"Carlstrom","sequence":"additional","affiliation":[{"name":"Stanford University"}]},{"given":"JaeWoong","family":"Chung","sequence":"additional","affiliation":[{"name":"Stanford University"}]},{"given":"Lance","family":"Hammond","sequence":"additional","affiliation":[{"name":"Stanford University"}]},{"given":"Christos","family":"Kozyrakis","sequence":"additional","affiliation":[{"name":"Stanford University"}]},{"given":"Kunle","family":"Olukotun","sequence":"additional","affiliation":[{"name":"Stanford University"}]}],"member":"320","published-online":{"date-parts":[[2005,6,20]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Intel Corporation VTune: a visual tuning environment. http:\/\/support.intel.com\/support\/performancetools\/vtune\/. Intel Corporation VTune: a visual tuning environment. http:\/\/support.intel.com\/support\/performancetools\/vtune\/."},{"key":"e_1_3_2_1_2_1","unstructured":"Stanford Parallel Applications for Shared Memory SPLASH. http:\/\/www-flash.stanford.edu\/apps\/SPLASH\/. Stanford Parallel Applications for Shared Memory SPLASH. http:\/\/www-flash.stanford.edu\/apps\/SPLASH\/."},{"key":"e_1_3_2_1_3_1","unstructured":"Java Grande Forum Java Grande Benchmark Suite. http:\/\/www.epcc.ed.ac.uk\/javagrande\/ 2000. Java Grande Forum Java Grande Benchmark Suite. http:\/\/www.epcc.ed.ac.uk\/javagrande\/ 2000."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339691"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.41"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/268998.266637"},{"volume-title":"Presentation at 2002 Embedded Processor Forum","year":"2002","author":"Broadcom Corporation","key":"e_1_3_2_1_7_1","unstructured":"Broadcom Corporation . The Broadcom BCM-1250 Multiprocessor . In Presentation at 2002 Embedded Processor Forum , April 2002 . Broadcom Corporation. The Broadcom BCM-1250 Multiprocessor. In Presentation at 2002 Embedded Processor Forum, April 2002."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/776261.776294"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/266800.266828"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/125826.126075"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1024393.1024395"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.5555\/998680.1006711"},{"volume-title":"Conference Record of Hot Chips 16","year":"2004","author":"Kongetira P.","key":"e_1_3_2_1_13_1","unstructured":"P. Kongetira , A 32-way multithreaded Sparc processor. In Conference Record of Hot Chips 16 , Stanford, CA , August 2004 . P. Kongetira, A 32-way multithreaded Sparc processor. In Conference Record of Hot Chips 16, Stanford, CA, August 2004."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/191995.192056"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/133057.133079"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/233013.233035"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2005.11"},{"volume-title":"Conference Record of Hot Chips 15 Symposium","year":"2003","author":"Kalla J. T. R.","key":"e_1_3_2_1_18_1","unstructured":"J. T. R. Kalla , B. Sinharoy . Simultaneous multi-threading implementation in POWER5 . In Conference Record of Hot Chips 15 Symposium , Stanford, CA , August 2003 . J. T. R. Kalla, B. Sinharoy. Simultaneous multi-threading implementation in POWER5. In Conference Record of Hot Chips 15 Symposium, Stanford, CA, August 2003."},{"volume-title":"Conference Record of Hot Chips 15 Symposium","year":"2003","author":"Raman R.","key":"e_1_3_2_1_19_1","unstructured":"R. Raman . UltraSparc Gemini : Dual CPU processor . In Conference Record of Hot Chips 15 Symposium , Palo Alto, CA , August 2003 . R. Raman. UltraSparc Gemini: Dual CPU processor. In Conference Record of Hot Chips 15 Symposium, Palo Alto, CA, August 2003."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.729790"},{"key":"e_1_3_2_1_21_1","unstructured":"Standard Performance Evaluation Corporation SPEC CPU Benchmarks. http:\/\/www.specbench.org\/ 1995--2000. Standard Performance Evaluation Corporation SPEC CPU Benchmarks. http:\/\/www.specbench.org\/ 1995--2000."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/223982.223990"},{"volume-title":"High-Performance Compilers for Parallel Computing","year":"1995","author":"Wolfe M.","key":"e_1_3_2_1_23_1","unstructured":"M. Wolfe . High-Performance Compilers for Parallel Computing . Addison-Wesley , 1995 . M. Wolfe. High-Performance Compilers for Parallel Computing. Addison-Wesley, 1995."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/263764.263796"},{"volume-title":"Performance analysis using the MIPS R10000 performance counters","year":"1996","author":"Zagha M.","key":"e_1_3_2_1_25_1","unstructured":"M. Zagha , B. Larson , S. Turner , and M. Itzkowitz . Performance analysis using the MIPS R10000 performance counters . 1996 . M. Zagha, B. Larson, S. Turner, and M. Itzkowitz. Performance analysis using the MIPS R10000 performance counters. 1996."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"crossref","first-page":"241","DOI":"10.1109\/HPCA.2001.903267","volume-title":"HPCA-7: Proceedings of the 7th International Symposium on High-Performance Computer Architecture","author":"Zilles C. B.","year":"2001","unstructured":"C. B. Zilles and G. S. Sohi . A programmable co-processor for profiling . In HPCA-7: Proceedings of the 7th International Symposium on High-Performance Computer Architecture , pages 241 -- 253 , 2001 . C. B. Zilles and G. S. Sohi. A programmable co-processor for profiling. In HPCA-7: Proceedings of the 7th International Symposium on High-Performance Computer Architecture, pages 241--253, 2001."}],"event":{"name":"ICS05: International Conference on Supercomputing 2005","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture"],"location":"Cambridge Massachusetts","acronym":"ICS05"},"container-title":["Proceedings of the 19th annual international conference on Supercomputing"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1088149.1088176","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,9]],"date-time":"2023-01-09T14:51:24Z","timestamp":1673275884000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1088149.1088176"}},"subtitle":["a transactional application profiling environment"],"short-title":[],"issued":{"date-parts":[[2005,6,20]]},"references-count":26,"alternative-id":["10.1145\/1088149.1088176","10.1145\/1088149"],"URL":"https:\/\/doi.org\/10.1145\/1088149.1088176","relation":{},"subject":[],"published":{"date-parts":[[2005,6,20]]},"assertion":[{"value":"2005-06-20","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}
