{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,7,24]],"date-time":"2024-07-24T17:53:32Z","timestamp":1721843612596},"reference-count":52,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100003968","name":"Iran National Science Foundation","doi-asserted-by":"publisher","award":["96006071"],"id":[{"id":"10.13039\/501100003968","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001659","name":"Deutsche Forschungsgemeinschaft","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001659","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2019,3]]},"DOI":"10.1109\/tvlsi.2018.2886326","type":"journal-article","created":{"date-parts":[[2019,1,11]],"date-time":"2019-01-11T19:58:32Z","timestamp":1547236712000},"page":"651-664","source":"Crossref","is-referenced-by-count":13,"title":["Estimating and Mitigating Aging Effects in Routing Network of FPGAs"],"prefix":"10.1109","volume":"27","author":[{"ORCID":"http:\/\/orcid.org\/0000-0002-3655-0501","authenticated-orcid":false,"given":"Behnam","family":"Khaleghi","sequence":"first","affiliation":[]},{"given":"Behzad","family":"Omidi","sequence":"additional","affiliation":[]},{"ORCID":"http:\/\/orcid.org\/0000-0002-5649-3102","authenticated-orcid":false,"given":"Hussam","family":"Amrouch","sequence":"additional","affiliation":[]},{"given":"Jorg","family":"Henkel","sequence":"additional","affiliation":[]},{"ORCID":"http:\/\/orcid.org\/0000-0002-0264-3865","authenticated-orcid":false,"given":"Hossein","family":"Asadi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1016\/bs.adcom.2018.04.002"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2636141"},{"key":"ref33","year":"2012","journal-title":"Virtex-6 FPGA Configurable Logic Block"},{"key":"ref32","first-page":"3d.1.1","article-title":"Connecting the physical and application level towards grasping aging effects","author":"amrouch","year":"2015","journal-title":"Proc IEEE Int Rel Phys Symp (IRPS)"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645511"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046195"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927201"},{"key":"ref36","year":"2017","journal-title":"7 Series FPGAs Data Sheet Overview"},{"key":"ref35","year":"2016","journal-title":"Nangate open cell library"},{"key":"ref34","year":"2016","journal-title":"Stratix IV Device Handbook"},{"key":"ref28","first-page":"9","article-title":"Automatic circuit design and modelling for heterogeneous FPGAs","author":"yazdanshenas","year":"2017","journal-title":"Proc IEEE Int Conf Field-Program Technol (FPT)"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2014.7001394"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/2617593"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2039370.2039384"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884574"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2013.6651926"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2015.7372547"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645497"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.887920"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2017.2725952"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.909795"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2007.910426"},{"key":"ref50","author":"albrecht","year":"2005","journal-title":"IWLS 2005 Benchmarks"},{"key":"ref51","article-title":"The RISC-V instruction set manual, volume I: Base user-level ISA","author":"waterman","year":"2011"},{"key":"ref52","article-title":"Logic synthesis and optimization benchmarks user guide, version 3.0","author":"yang","year":"1991"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884870"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.37"},{"key":"ref40","doi-asserted-by":"crossref","first-page":"111","DOI":"10.1109\/FPGA.1995.242049","article-title":"pathfinder: a negotiation-based performance-driven router for fpgas","author":"mcmurchie","year":"1995","journal-title":"Third International ACM Symposium on Field-Programmable Gate Arrays"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2295799"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2007.70235"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2016.7577341"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2009.5377640"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2016.7577328"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2012.6412136"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2013.2253795"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2010.88"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2012.04.005"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2040125"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2004.03.019"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2012.6241840"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898082"},{"key":"ref7","first-page":"370","article-title":"NBTI-aware synthesis of digital circuits","author":"kumar","year":"2007","journal-title":"Proc 44th Annu Design Autom Conf"},{"key":"ref49","author":"mishchenko","year":"2007","journal-title":"ABC A System for Sequential Synthesis and Verification"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155622"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1145\/329166.329208"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2011.69"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2010.31"},{"key":"ref47","year":"2013","journal-title":"Predictive Technology Model (PTM)"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311199"},{"key":"ref41","volume":"497","author":"betz","year":"2012","journal-title":"Architecture and CAD for Deep-Submicron FPGAs"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/ReCoSoC.2011.5981545"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2015.2406791"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8649697\/08610235.pdf?arnumber=8610235","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T21:10:23Z","timestamp":1657746623000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8610235\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,3]]},"references-count":52,"journal-issue":{"issue":"3"},"URL":"http:\/\/dx.doi.org\/10.1109\/tvlsi.2018.2886326","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,3]]}}}
