iBet uBet web content aggregator. Adding the entire web to your favor.
iBet uBet web content aggregator. Adding the entire web to your favor.



Link to original content: https://api.crossref.org/works/10.1109/TVLSI.2011.2168834
{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,6,10]],"date-time":"2024-06-10T17:51:18Z","timestamp":1718041878312},"reference-count":33,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2012,11,1]],"date-time":"2012-11-01T00:00:00Z","timestamp":1351728000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2012,11]]},"DOI":"10.1109\/tvlsi.2011.2168834","type":"journal-article","created":{"date-parts":[[2011,10,17]],"date-time":"2011-10-17T20:46:58Z","timestamp":1318884418000},"page":"2094-2103","source":"Crossref","is-referenced-by-count":23,"title":["Fast Power- and Slew-Aware Gated Clock Tree Synthesis"],"prefix":"10.1109","volume":"20","author":[{"given":"Jingwei","family":"Lu","sequence":"first","affiliation":[]},{"given":"Wing-Kai","family":"Chow","sequence":"additional","affiliation":[]},{"given":"Chiu-Wing","family":"Sham","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/1735023.1735058"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/1514932.1514965"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/1297666.1297686"},{"key":"ref30","doi-asserted-by":"crossref","first-page":"715","DOI":"10.1109\/43.924825","article-title":"Gated clock routing for low-power microprocessor design","volume":"20","author":"oh","year":"2001","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1990.112223"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/157485.165019"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.847942"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/43.658565"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/43.602470"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"612","DOI":"10.1145\/157485.165066","article-title":"a clustering-based optimization algorithm in zero-skew routings","author":"edahiro","year":"1993","journal-title":"30th ACM\/IEEE Design Automation Conference"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2004.1283704"},{"key":"ref17","first-page":"467","article-title":"A dual-MST approach for clock network synthesis","author":"lu","year":"2010","journal-title":"Proc Asia South Pacific Design Autom Conf"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837297"},{"key":"ref19","first-page":"389","article-title":"Minimizing clock latency range in robust clock tree synthesis","author":"liu","year":"2010","journal-title":"Proc Asia South Pacific Design Autom Conf"},{"key":"ref28","doi-asserted-by":"crossref","first-page":"279","DOI":"10.1145\/566408.566481","article-title":"Activity-sensitive clock tree construction for low power","author":"chen","year":"2002","journal-title":"Proc Int Symp Low Power Electron Design"},{"key":"ref4","first-page":"41","article-title":"Minimum path-length equi-distant routing","author":"edahiro","year":"1992","journal-title":"Proc IEEE Asia-Pacific Conf Circuits Syst"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/43.924824"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1990.114920"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1063\/1.1697872"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.1998.655933"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"322","DOI":"10.1145\/127601.127688","article-title":"High-performance clock routing based on recursive geometric matching","author":"kahng","year":"1991","journal-title":"28th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.1992.270316"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1991.185269"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.1998.669476"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"799","DOI":"10.1109\/82.204128","article-title":"Zero skew clock routing with minimum wirelength","volume":"39","author":"chao","year":"1992","journal-title":"IEEE Trans Circuits Syst II Analog Digit Signal Process"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/293625.293628"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391653"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065766"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/775988.775989"},{"key":"ref24","doi-asserted-by":"crossref","first-page":"176","DOI":"10.1145\/313817.313913","article-title":"Challenges in clockgating for a low power ASIC methodology","author":"garrett","year":"1999","journal-title":"Proceedings 1999 International Symposium on Low Power Electronics and Design (Cat No 99TH8477) LPE"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.824307"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1995.479992"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2030156"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6252108\/06046234.pdf?arnumber=6046234","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:47:36Z","timestamp":1633909656000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6046234\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,11]]},"references-count":33,"journal-issue":{"issue":"11"},"URL":"http:\/\/dx.doi.org\/10.1109\/tvlsi.2011.2168834","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,11]]}}}