{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,20]],"date-time":"2024-09-20T16:42:16Z","timestamp":1726850536227},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2021,11,1]],"date-time":"2021-11-01T00:00:00Z","timestamp":1635724800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,11,1]],"date-time":"2021-11-01T00:00:00Z","timestamp":1635724800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,11,1]],"date-time":"2021-11-01T00:00:00Z","timestamp":1635724800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Key Research and Development Program of China","doi-asserted-by":"publisher","award":["2018YFB1702500"],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100012282","name":"Beijing Innovation Center for Future Chips, Tsinghua University","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100012282","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2021,11]]},"DOI":"10.1109\/tcad.2020.3041380","type":"journal-article","created":{"date-parts":[[2020,11,30]],"date-time":"2020-11-30T21:05:38Z","timestamp":1606770338000},"page":"2237-2250","source":"Crossref","is-referenced-by-count":2,"title":["Reducing SRAM Reading Power With Column Data Segment and Weights Correlation Enhancement for CNN Processing"],"prefix":"10.1109","volume":"40","author":[{"ORCID":"http:\/\/orcid.org\/0000-0002-2469-1286","authenticated-orcid":false,"given":"Han","family":"Xu","sequence":"first","affiliation":[]},{"ORCID":"http:\/\/orcid.org\/0000-0003-2316-7017","authenticated-orcid":false,"given":"Ziwei","family":"Li","sequence":"additional","affiliation":[]},{"given":"Ziru","family":"Li","sequence":"additional","affiliation":[]},{"ORCID":"http:\/\/orcid.org\/0000-0002-7989-6297","authenticated-orcid":false,"given":"Deliang","family":"Fan","sequence":"additional","affiliation":[]},{"ORCID":"http:\/\/orcid.org\/0000-0002-5054-9590","authenticated-orcid":false,"given":"Fei","family":"Qiao","sequence":"additional","affiliation":[]},{"ORCID":"http:\/\/orcid.org\/0000-0003-3189-7562","authenticated-orcid":false,"given":"Qi","family":"Wei","sequence":"additional","affiliation":[]},{"ORCID":"http:\/\/orcid.org\/0000-0001-5519-3143","authenticated-orcid":false,"given":"Li","family":"Luo","sequence":"additional","affiliation":[]},{"given":"Xinjun","family":"Liu","sequence":"additional","affiliation":[]},{"ORCID":"http:\/\/orcid.org\/0000-0003-2421-353X","authenticated-orcid":false,"given":"Huazhong","family":"Yang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref30","first-page":"4107","article-title":"Binarized neural networks","author":"hubara","year":"2016","journal-title":"Advances in neural information processing systems"},{"key":"ref10","first-page":"222","article-title":"An always-on 3.8?J\/86% CIFAR-10 mixed-signal binary CNN processor with all memory on chip in 28nm CMOS","author":"bankman","year":"2018","journal-title":"Proc IEEE Int Solid-State Circuits Conf (ISSCC)"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2642198"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2822703"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2782087"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2934583.2934619"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2731814"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2018.8618508"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED48828.2020.9136993"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/5.726791"},{"key":"ref19","first-page":"1097","article-title":"ImageNet classification with deep convolutional neural networks","author":"krizhevsky","year":"2012","journal-title":"Advances in neural information processing systems"},{"key":"ref28","author":"weste","year":"2015","journal-title":"CMOS VLSI Design A Circuits and Systems Perspective"},{"key":"ref4","author":"simonyan","year":"2014","journal-title":"Very Deep Convolutional Networks for Large-scale Image Recognition"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2012.2231018"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2007.2"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310398"},{"key":"ref29","author":"li","year":"2020","journal-title":"Improving efficiency in neural network accelerator using operands hamming distance optimization"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870349"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908005"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2006.1696322"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1494076"},{"key":"ref1","author":"han","year":"2015","journal-title":"Deep compression Compressing deep neural networks with pruning trained quantization and huffman coding"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2647868.2654889"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.94"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2000249"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2280310"},{"key":"ref26","first-page":"332","article-title":"A sub-200mV 6T SRAM in 0.13?m CMOS","author":"bo","year":"2007","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090796"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9579466\/09273078.pdf?arnumber=9273078","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:49:32Z","timestamp":1652194172000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9273078\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,11]]},"references-count":30,"journal-issue":{"issue":"11"},"URL":"http:\/\/dx.doi.org\/10.1109\/tcad.2020.3041380","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,11]]}}}