iBet uBet web content aggregator. Adding the entire web to your favor.
iBet uBet web content aggregator. Adding the entire web to your favor.



Link to original content: https://api.crossref.org/works/10.1109/L-CA.2011.3
{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,12,5]],"date-time":"2022-12-05T20:31:28Z","timestamp":1670272288073},"reference-count":13,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2011,1,1]],"date-time":"2011-01-01T00:00:00Z","timestamp":1293840000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Comput. Arch. Lett."],"published-print":{"date-parts":[[2011,1]]},"DOI":"10.1109\/l-ca.2011.3","type":"journal-article","created":{"date-parts":[[2011,2,11]],"date-time":"2011-02-11T21:40:57Z","timestamp":1297460457000},"page":"12-15","source":"Crossref","is-referenced-by-count":4,"title":["DCC: A Dependable Cache Coherence Multicore Architecture"],"prefix":"10.1109","volume":"10","author":[{"given":"Omer","family":"Khan","sequence":"first","affiliation":[]},{"given":"Mieszko","family":"Lis","sequence":"additional","affiliation":[]},{"given":"Yildiz","family":"Sinangil","sequence":"additional","affiliation":[]},{"given":"Srinivas","family":"Devadas","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IPPS.1995.395974"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416635"},{"key":"ref12","article-title":"System-level optimizations for memory access in the execution migration machine (EM2)","author":"shim","year":"2011","journal-title":"Workshop on Computer Arch and Operating System co-design"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555793"},{"key":"ref4","article-title":"EM2: A Scalable Shared-Memory Multicore Architecture","author":"khan","year":"2010","journal-title":"MIT-CSAIL-TR-2010-030"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555769"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555779"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2007.375263"},{"key":"ref8","article-title":"Reducing memory and traffic requirements for scalable directory-based cache coherence schemes","author":"gupta","year":"1990","journal-title":"ICPP"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/2.55500"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.34"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.110"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/237090.237205"}],"container-title":["IEEE Computer Architecture Letters"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10208\/5892921\/05710653.pdf?arnumber=5710653","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:28:19Z","timestamp":1638217699000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5710653\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,1]]},"references-count":13,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/l-ca.2011.3","relation":{},"ISSN":["1556-6056"],"issn-type":[{"value":"1556-6056","type":"print"}],"subject":[],"published":{"date-parts":[[2011,1]]}}}