iBet uBet
web content aggregator. Adding the entire web to your favor.
Link to original content:
https://api.crossref.org/works/10.1109/JSSC.2004.827806
{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,9]],"date-time":"2024-09-09T09:15:16Z","timestamp":1725873316205},"reference-count":8,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2004,6,1]],"date-time":"2004-06-01T00:00:00Z","timestamp":1086048000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2004,6]]},"DOI":"10.1109\/jssc.2004.827806","type":"journal-article","created":{"date-parts":[[2004,6,2]],"date-time":"2004-06-02T20:48:32Z","timestamp":1086209312000},"page":"941-951","source":"Crossref","is-referenced-by-count":23,"title":["A 1.8-V 700-mb\/s\/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration"],"prefix":"10.1109","volume":"39","author":[{"family":"Changsik Yoo","sequence":"first","affiliation":[]},{"family":"Kye-Hyun Kyung","sequence":"additional","affiliation":[]},{"family":"Kyunam Lim","sequence":"additional","affiliation":[]},{"family":"Hi-Choon Lee","sequence":"additional","affiliation":[]},{"family":"Joon-Wan Chai","sequence":"additional","affiliation":[]},{"family":"Nak-Won Heo","sequence":"additional","affiliation":[]},{"family":"Dong-Jin Lee","sequence":"additional","affiliation":[]},{"family":"Chang-Hyun Kim","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","year":"0","journal-title":"On-Line Information on DDR-II SDRAM"},{"key":"ref3","first-page":"68","article-title":"digitally-controlled dll and i\/o circuits for 500 mb\/s\/pin
$\\times\\,$<\/tex><\/formula>16 ddr sdram","author":"lee","year":"2001","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref6","first-page":"382","article-title":"a 113
$\\hbox{mm}^{2}$ <\/tex><\/formula> 600 mb\/s\/pin 512 mb ddr2 sdram with vertically-folded bitline architecture","author":"kirihata","year":"2001","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2002.1015058"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2002.1015061"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/4.535414"},{"key":"ref2","year":"2003","journal-title":"K4H511638B 512 Mb 400 Mbps DDR SDRAM Databook"},{"key":"ref1","year":"2002","journal-title":"K4R521669A-FCN9 512 Mb RAMBUS DRAM Databook"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4\/28938\/01302271.pdf?arnumber=1302271","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:27:50Z","timestamp":1638217670000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1302271\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004,6]]},"references-count":8,"journal-issue":{"issue":"6"},"URL":"http:\/\/dx.doi.org\/10.1109\/jssc.2004.827806","relation":{},"ISSN":["0018-9200"],"issn-type":[{"value":"0018-9200","type":"print"}],"subject":[],"published":{"date-parts":[[2004,6]]}}}
