iBet uBet web content aggregator. Adding the entire web to your favor.
iBet uBet web content aggregator. Adding the entire web to your favor.



Link to original content: https://api.crossref.org/works/10.1109/ISQED.2019.8697441
{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T05:20:13Z","timestamp":1725600013606},"reference-count":28,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,3]]},"DOI":"10.1109\/isqed.2019.8697441","type":"proceedings-article","created":{"date-parts":[[2019,4,26]],"date-time":"2019-04-26T03:49:36Z","timestamp":1556250576000},"page":"145-150","source":"Crossref","is-referenced-by-count":1,"title":["MAPIM: Mat Parallelism for High Performance Processing in Non-volatile Memory Architecture"],"prefix":"10.1109","author":[{"given":"Joonseop","family":"Sim","sequence":"first","affiliation":[]},{"given":"Minsu","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Yeseong","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Saransh","family":"Gupta","sequence":"additional","affiliation":[]},{"given":"Behnam","family":"Khaleghi","sequence":"additional","affiliation":[]},{"given":"Tajana","family":"Rosing","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1002\/aelm.201400056"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2017.7858415"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001140"},{"key":"ref13","first-page":"168","article-title":"Fine-granularity tile-level parallelism in nonvolatile memory architecture with two-dimensional bank subdivision","author":"poremba","year":"2016","journal-title":"Proc 53rd Annu Design Autom Conf"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540717"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124545"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176872"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2014.6853217"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00054"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2017.2654339"},{"journal-title":"CMOS VLSI Design","year":"2010","author":"weste","key":"ref28"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898064"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370865"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2994149"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2009.5226356"},{"key":"ref5","doi-asserted-by":"crossref","DOI":"10.1109\/TCSII.2014.2357292","article-title":"Magicmemristor-aided logic","author":"kvatinsky","year":"2014","journal-title":"IEEE Transactions on Circuits and Systems II Express Briefs"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124544"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2015.2434872"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750385"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3123977"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MIS.2013.39"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669155"},{"journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","article-title":"Nvsim: A circuit-level performance, energy, and area model for emerging nonvolatile memory","year":"2012","author":"dong","key":"ref22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2366231.2337202"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2018.8357265"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2012.82"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2433536"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1116\/1.4865572"}],"event":{"name":"2019 20th International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2019,3,6]]},"location":"Santa Clara, CA, USA","end":{"date-parts":[[2019,3,7]]}},"container-title":["20th International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8682005\/8697223\/08697441.pdf?arnumber=8697441","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,15]],"date-time":"2022-07-15T03:11:52Z","timestamp":1657854712000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8697441\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,3]]},"references-count":28,"URL":"http:\/\/dx.doi.org\/10.1109\/isqed.2019.8697441","relation":{},"subject":[],"published":{"date-parts":[[2019,3]]}}}