{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T16:58:30Z","timestamp":1725469110458},"reference-count":12,"publisher":"IEEE Comput. Soc. Press","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/eurdac.1996.558227","type":"proceedings-article","created":{"date-parts":[[2002,12,24]],"date-time":"2002-12-24T01:52:43Z","timestamp":1040694763000},"page":"342-347","source":"Crossref","is-referenced-by-count":17,"title":["Timing optimization by an improved redundancy addition and removal technique"],"prefix":"10.1109","author":[{"given":"L.A.","family":"Entrena","sequence":"first","affiliation":[]},{"given":"J.A.","family":"Espejo","sequence":"additional","affiliation":[]},{"given":"E.","family":"Olias","sequence":"additional","affiliation":[]},{"given":"J.","family":"Uceda","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1994.629734"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"308","DOI":"10.1145\/196244.196388","article-title":"layout driven logic synthesis for fpgas","author":"chang","year":"1994","journal-title":"31st Design Automation Conference"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1988.122511"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/43.391740"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1990.114878"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1994.629735"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/217474.217608"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1992.527905"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/224818.224904"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1993.580074"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1992.227754"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/EDAC.1993.386447"}],"event":{"name":"EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition","acronym":"EURDAC-96","location":"Geneva, Switzerland"},"container-title":["Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx3\/4063\/12120\/00558227.pdf?arnumber=558227","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T16:36:16Z","timestamp":1497544576000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/558227\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/eurdac.1996.558227","relation":{},"subject":[]}}
