{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T07:37:36Z","timestamp":1729669056100,"version":"3.28.0"},"reference-count":24,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,9]]},"DOI":"10.1109\/dsd.2010.69","type":"proceedings-article","created":{"date-parts":[[2010,11,10]],"date-time":"2010-11-10T15:57:59Z","timestamp":1289404679000},"page":"331-338","source":"Crossref","is-referenced-by-count":2,"title":["Adaptive Cache Memories for SMT Processors"],"prefix":"10.1109","author":[{"given":"Sonia","family":"Lopez","sequence":"first","affiliation":[]},{"given":"Oscar","family":"Garnica","sequence":"additional","affiliation":[]},{"given":"David H.","family":"Albonesi","sequence":"additional","affiliation":[]},{"given":"Steven","family":"Dropsho","sequence":"additional","affiliation":[]},{"given":"Juan","family":"Lanchares","sequence":"additional","affiliation":[]},{"given":"Jose I.","family":"Hidalgo","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003573"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694788"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.18"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2002.1106013"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-69338-3_10"},{"key":"ref15","first-page":"164","article-title":"Balancing Throughput and Fairness in SMT Processors","author":"luo","year":"2001","journal-title":"Proc IEEE Int l Symp Performance Analysis of Systems and Software"},{"journal-title":"Proc Symp on VLSI Circuits Short Course on Physical Design for Low-Power and High-Performance Microprocessor Circuits","article-title":"Circuit Design of XScale™ Microprocessors","year":"2001","author":"clark","key":"ref16"},{"journal-title":"Transmeta Corporation Tech Rep","article-title":"LongRunTM Power Management","year":"2001","author":"fleischmann","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ARVLSI.1997.634845"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2004.1299297"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2003.1237998"},{"key":"ref3","first-page":"1","article-title":"Hyper-Threading Technology Architecture and Microarchitecture","volume":"6","author":"marr","year":"2002","journal-title":"Intel Technology Journal"},{"key":"ref6","first-page":"31","article-title":"Front-End Policies for Improved Issue Efficiency in SMT Processors","author":"ei-moursy","year":"2003","journal-title":"Proc 8th Int l Symp High-Performance Computer Architecture"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2001.991129"},{"key":"ref8","first-page":"171","article-title":"Dy-namically Controlled Resource Allocation in SMT Processors","author":"cazorla","year":"2004","journal-title":"Proc 37th Ann IEEE\/ACM Int'l Symp on Microarchitecture"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"70","DOI":"10.1007\/978-3-540-39707-6_6","article-title":"Improving Memory Latency Aware Fetch Policies for SMT Processors","author":"cazorla","year":"2003","journal-title":"Proc Int l Symp High Performance Computing"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/232973.232993"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/285930.286011"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2002.995696"},{"key":"ref20","doi-asserted-by":"crossref","first-page":"14","DOI":"10.1145\/871656.859621","article-title":"Profile-Based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain Microprocessor","author":"magklis","year":"2003","journal-title":"Proc 30th Int'l Symp on Computer Architecture"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1999.809463"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2002.1176263"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/268806.268810"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/4.509850"}],"event":{"name":"2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD)","start":{"date-parts":[[2010,9,1]]},"location":"Lille, France","end":{"date-parts":[[2010,9,3]]}},"container-title":["2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5613535\/5615428\/05615592.pdf?arnumber=5615592","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,19]],"date-time":"2017-06-19T12:00:53Z","timestamp":1497873653000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5615592\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,9]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/dsd.2010.69","relation":{},"subject":[],"published":{"date-parts":[[2010,9]]}}}
