{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T17:51:44Z","timestamp":1729619504323,"version":"3.28.0"},"reference-count":8,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,12]]},"DOI":"10.1109\/apccas.2010.5774881","type":"proceedings-article","created":{"date-parts":[[2011,5,27]],"date-time":"2011-05-27T13:30:45Z","timestamp":1306503045000},"page":"304-307","source":"Crossref","is-referenced-by-count":3,"title":["CAM puzzle: A power model and function-based circuit segment method of Content Addressable Memory"],"prefix":"10.1109","author":[{"given":"Kam-Tou","family":"Sio","sequence":"first","affiliation":[]},{"given":"Feipei","family":"Lai","sequence":"additional","affiliation":[]},{"given":"Chin-Hung","family":"Peng","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/APCCAS.2002.1115248"},{"key":"ref3","first-page":"824","article-title":"Architectural power models for SRAM and CAM structures based on hybrid analytical\/empirical techniques","author":"liang","year":"2007","journal-title":"Computer-Aided Design"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.864128"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"654","DOI":"10.1109\/JSSC.2003.809515","article-title":"A low-power precomputation-based fully parallel content-addressable memory","volume":"38","author":"lin","year":"2003","journal-title":"IEEE Journal of Solid-State Circuits (JSSC)"},{"key":"ref8","first-page":"3","article-title":"Mibench: A free, commercially representative embedded benchmark suite","author":"guthaus","year":"2001","journal-title":"Proc IEEE Int Workshop Workload Characterization"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.915514"},{"key":"ref2","first-page":"926","article-title":"Power modeling and low-power design of content addressable memories","volume":"4","author":"hsiao","year":"2001","journal-title":"Proc IEEE Int Symp Circuits and Systems (ISCAS)"},{"key":"ref1","first-page":"316","article-title":"Synthesis and design of parameter extractors for low-power precomputation-based content-addressable memory using gate-block selection algorithm","author":"hsieh","year":"2008","journal-title":"Asia and South Pacific Design Automation Conference"}],"event":{"name":"APCCAS 2010-2010 IEEE Asia Pacific Conference on Circuits and Systems","start":{"date-parts":[[2010,12,6]]},"location":"Kuala Lumpur, Malaysia","end":{"date-parts":[[2010,12,9]]}},"container-title":["2010 IEEE Asia Pacific Conference on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5767825\/5774732\/05774881.pdf?arnumber=5774881","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,19]],"date-time":"2017-06-19T20:54:20Z","timestamp":1497905660000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5774881\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,12]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/apccas.2010.5774881","relation":{},"subject":[],"published":{"date-parts":[[2010,12]]}}}
