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Link to original content: https://api.crossref.org/works/10.1109/5.920582
{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,7,6]],"date-time":"2024-07-06T04:36:15Z","timestamp":1720240575746},"reference-count":66,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2001,4,1]],"date-time":"2001-04-01T00:00:00Z","timestamp":986083200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Proc. IEEE"],"published-print":{"date-parts":[[2001,4]]},"DOI":"10.1109\/5.920582","type":"journal-article","created":{"date-parts":[[2002,8,24]],"date-time":"2002-08-24T18:17:23Z","timestamp":1030213043000},"page":"529-555","source":"Crossref","is-referenced-by-count":163,"title":["On-chip wiring design challenges for gigahertz operation"],"prefix":"10.1109","volume":"89","author":[{"given":"A.","family":"Deutsch","sequence":"first","affiliation":[]},{"given":"P.W.","family":"Coteus","sequence":"additional","affiliation":[]},{"given":"G.V.","family":"Kopcsay","sequence":"additional","affiliation":[]},{"given":"H.H.","family":"Smith","sequence":"additional","affiliation":[]},{"given":"C.W.","family":"Surovic","sequence":"additional","affiliation":[]},{"given":"B.L.","family":"Krauter","sequence":"additional","affiliation":[]},{"given":"D.C.","family":"Edelstein","sequence":"additional","affiliation":[]},{"given":"P.L.","family":"Restle","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/EPEP.1998.734041"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1147\/rd.251.0025"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/EPEP.1996.564770"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/96.533888"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/EPEP.1997.634037"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2000.852885"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/22.3545"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/EPEP.1993.394596"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/22.310584"},{"key":"ref34","first-page":"27","author":"millman","year":"1965","journal-title":"Pulse Digital and Switching Waveforms"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/6040.784478"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1109\/16.661220"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/EPEP.2000.895555"},{"key":"ref28","first-page":"381","volume":"ii","author":"weber","year":"1956","journal-title":"Linear Transient Analysis"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1109\/16.661220"},{"key":"ref27","doi-asserted-by":"crossref","first-page":"1836","DOI":"10.1109\/22.641781","article-title":"when are transmission-line effects important for on-chip interconnections","author":"deutsch","year":"1997","journal-title":"IEEE Trans Microwave Theory and Techniques"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1109\/101.666589"},{"key":"ref65","article-title":"system chip challenges and opportunities","author":"pogge","year":"1998","journal-title":"Digest IMAPS Advanced Technology Workshop on Next Generation IC and Package Design"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.1998.687985"},{"key":"ref66","article-title":"packaging provides viable alternatives to soc","author":"baliga","year":"2000","journal-title":"Semiconductor Int"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2000.839707"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2000.839702"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.1999.824294"},{"key":"ref22","first-page":"172","article-title":"on-chip inductance modeling of vlsi interconnects","author":"qi","year":"2000","journal-title":"Proc Dig 2000 IEEE Int Solid-State Circuits Conf"},{"key":"ref21","first-page":"566","article-title":"Layout techniques for minimizing on-chip interconnect self-inductance","author":"massoud","year":"1998","journal-title":"Proceedings 1998 Design and Automation Conference 35th DAC (Cat No 98CH36175) DAC"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1147\/rd.344.0601"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/EPEP.2000.895554"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/5.362754"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.1998.746358"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2000.839758"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/EPEP.1997.634038"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2000.853160"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2000.839754"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/EPEP.2000.895550"},{"key":"ref56","first-page":"472","article-title":"ultra-wide bandwidth instrument product based on josephson junctions","author":"hanson","year":"1987","journal-title":"Proc Int Conf Computer Design"},{"key":"ref55","author":"manufactured by ggb industries inc p o box 10958","year":"0"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/19.106281"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/EPEP.2000.895523"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/EPEP.2000.895510"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/96.533884"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/EPEP.1996.564820"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1147\/rd.165.0470"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1997.643366"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/EPEP.1998.734050"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/EPEP.1999.819198"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1147\/rd.395.0547"},{"key":"ref16","author":"cheng","year":"2000","journal-title":"Interconnect Analysis and Synthesis"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/EPEP.1998.733992"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/4.760372"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2000.839760"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/6040.784477"},{"key":"ref3","author":"matick","year":"1969","journal-title":"Transmission Lines for Digital and Communication Networks"},{"key":"ref6","first-page":"491","article-title":"a novel vlsi fabric for deep submicron applications","author":"khatri","year":"1998","journal-title":"Proc Dig 36th Design Automation Conf"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/EPEP.2000.895553"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/EPEP.1996.564769"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/55.596927"},{"key":"ref7","first-page":"921","article-title":"on-chip inductance issues in multiconductor systems","author":"morton","year":"1998","journal-title":"Proc Dig 36th Design Automation Conf"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/EPEP.1998.733493"},{"key":"ref46","first-page":"138","article-title":"applications of on-chip samplers for test and measurement of integrated circuits","author":"ho","year":"1998","journal-title":"Proc Dig IEEE Symp VLSI Circuits"},{"key":"ref45","first-page":"11","article-title":"ic packaging and test","author":"frisch","year":"1999","journal-title":"Proc Dig IMAPS Advanced Technology Workshop on Next Generation IC and Package Design"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2000.839757"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/4.135341"},{"key":"ref42","doi-asserted-by":"crossref","first-page":"303","DOI":"10.1145\/277044.277133","article-title":"Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis","author":"krauter","year":"1998","journal-title":"Proceedings 1998 Design and Automation Conference 35th DAC (Cat No 98CH36175) DAC"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/22.3513"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/EPEP.1999.819222"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/MWSYM.1996.512297"}],"container-title":["Proceedings of the IEEE"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5\/19892\/00920582.pdf?arnumber=920582","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:08:23Z","timestamp":1638216503000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/920582\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2001,4]]},"references-count":66,"journal-issue":{"issue":"4"},"URL":"http:\/\/dx.doi.org\/10.1109\/5.920582","relation":{},"ISSN":["0018-9219"],"issn-type":[{"value":"0018-9219","type":"print"}],"subject":[],"published":{"date-parts":[[2001,4]]}}}