{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,22]],"date-time":"2024-08-22T01:33:36Z","timestamp":1724290416881},"reference-count":109,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[1998,1,1]],"date-time":"1998-01-01T00:00:00Z","timestamp":883612800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Proc. IEEE"],"published-print":{"date-parts":[[1998]]},"DOI":"10.1109\/5.705525","type":"journal-article","created":{"date-parts":[[2002,8,24]],"date-time":"2002-08-24T20:26:37Z","timestamp":1030220797000},"page":"1819-1838","source":"Crossref","is-referenced-by-count":174,"title":["Defect tolerance in VLSI circuits: techniques and yield analysis"],"prefix":"10.1109","volume":"86","author":[{"given":"I.","family":"Koren","sequence":"first","affiliation":[]},{"given":"Z.","family":"Koren","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/MCD.1985.6311990"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/4.62132"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1982.1051772"},{"key":"ref32","author":"gyvez","year":"0","journal-title":"IC Manufacturability The Art of Process and Design Integration"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-3158-6"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/43.127625"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/66.382282"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/92.273147"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/12.75138"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1986.13492"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1986.1052528"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1016\/0038-1101(85)90125-X"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/16.2435"},{"key":"ref20","year":"1994","journal-title":"EDA CircuitBench user s guide"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/5.63298"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.1995.476931"},{"key":"ref24","doi-asserted-by":"crossref","first-page":"1727","DOI":"10.1109\/T-ED.1985.22187","article-title":"role of defect size distribution in yield modeling","volume":"32","author":"ferris-prabhu","year":"1985","journal-title":"IEEE Transactions on Electron Devices"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1990.112450"},{"key":"ref101","doi-asserted-by":"publisher","DOI":"10.1117\/12.284707"},{"key":"ref26","author":"ferris-prabhu","year":"1992","journal-title":"Introduction to Semiconductor Device Yield Modeling"},{"key":"ref100","doi-asserted-by":"publisher","DOI":"10.1109\/4.475716"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/MCD.1987.6323237"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/92.285750"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/ICISS.1996.552434"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-6799-8_17"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.1997.628304"},{"key":"ref57","doi-asserted-by":"crossref","author":"lengauer","year":"1990","journal-title":"Combinational Algorithms for Integrated Circuit Layout","DOI":"10.1007\/978-3-322-92106-2"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/43.240078"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/12.123398"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/ICWSI.1992.171793"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.1997.628322"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/92.555982"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/4.499733"},{"key":"ref4","article-title":"yield and reliability","author":"bertram","year":"1988","journal-title":"VLSI Technology"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1996.545672"},{"key":"ref6","first-page":"383","article-title":"symbolic layout compaction review","author":"boyer","year":"1988","journal-title":"Proc 27th ACM\/IEEE Design Automation Conf"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/2.129043"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.1995.476950"},{"key":"ref7","first-page":"31","article-title":"rye: a realistic yield simulator for vlsic structural failures","author":"chen","year":"1987","journal-title":"Proc IEEE Int Test Conf"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/12.277291"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.1995.522926"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/4.330"},{"key":"ref45","first-page":"91","article-title":"the effect of scaling on the yield of vlsi circuits","author":"koren","year":"1988","journal-title":"Yield Modeling and Defect Tolerance in VLSI"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/2.56854"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-6799-8_1"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1984.5009312"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/4.245589"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1987.1676906"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1986.13532"},{"key":"ref73","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1986.13531"},{"key":"ref72","doi-asserted-by":"publisher","DOI":"10.1109\/ASMC.1995.484386"},{"key":"ref71","doi-asserted-by":"publisher","DOI":"10.1109\/66.56568"},{"key":"ref70","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1964.3442"},{"key":"ref76","author":"negrini","year":"1989","journal-title":"Fault Tolerance Through Reconfiguration in VLSI and WSI Srrays"},{"key":"ref77","doi-asserted-by":"publisher","DOI":"10.1002\/eej.4390920619"},{"key":"ref74","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.1995.476933"},{"key":"ref75","doi-asserted-by":"publisher","DOI":"10.1109\/4.121559"},{"key":"ref78","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1977.1050952"},{"key":"ref79","doi-asserted-by":"crossref","first-page":"795","DOI":"10.1145\/74382.74532","article-title":"dtr: a defect-tolerant routing algorithm","author":"pitaksanonkul","year":"1989","journal-title":"26th ACM\/IEEE Design Automation Conference"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/12.338099"},{"key":"ref62","first-page":"100","article-title":"mcyield: a cad tool for functional yield projections","author":"lorenzetti","year":"1990","journal-title":"Proc IEEE Int Workshop on Defect and Fault Tolerance in VLSI Systems"},{"key":"ref61","article-title":"the effect of channel router algorithms on chip yield","author":"lorenzetti","year":"1990","journal-title":"MCNC International Workshop on Layout Synthesis"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1109\/ICWSI.1995.515463"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1109\/5.52217"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1985.1270112"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1109\/4.192046"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1986.1270182"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1984.12917"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.1995.476934"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1109\/12.21146"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/43.177399"},{"key":"ref95","doi-asserted-by":"publisher","DOI":"10.1147\/rd.284.0461"},{"key":"ref109","author":"yung","year":"1995"},{"key":"ref94","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1983.12619"},{"key":"ref108","doi-asserted-by":"publisher","DOI":"10.1109\/WAFER.1989.47538"},{"key":"ref107","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1996.542308"},{"key":"ref93","doi-asserted-by":"publisher","DOI":"10.1109\/66.388016"},{"key":"ref92","doi-asserted-by":"publisher","DOI":"10.1016\/0038-1101(82)90161-7"},{"key":"ref106","doi-asserted-by":"publisher","DOI":"10.1109\/4.487996"},{"key":"ref91","doi-asserted-by":"publisher","DOI":"10.1016\/0038-1101(81)90006-X"},{"key":"ref105","doi-asserted-by":"publisher","DOI":"10.1109\/43.3187"},{"key":"ref104","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1988.14729"},{"key":"ref90","doi-asserted-by":"publisher","DOI":"10.1147\/rd.243.0398"},{"key":"ref103","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-1931-4"},{"key":"ref102","doi-asserted-by":"publisher","DOI":"10.1109\/66.382276"},{"key":"ref98","doi-asserted-by":"publisher","DOI":"10.1147\/rd.332.0174"},{"key":"ref99","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-6799-8_22"},{"key":"ref96","doi-asserted-by":"publisher","DOI":"10.1147\/rd.291.0087"},{"key":"ref97","doi-asserted-by":"publisher","DOI":"10.1147\/rd.303.0326"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.1992.224342"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.1993.595768"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.1994.630019"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/66.382281"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1117\/12.250850"},{"key":"ref15","author":"ciciani","year":"1998","journal-title":"Manufacturing Yield Evaluation of VLSI\/WSI Systems"},{"key":"ref82","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1978.1051122"},{"key":"ref16","first-page":"83","article-title":"a yield enhancement methodology for custom vlsi manufacturing","volume":"4","author":"collica","year":"1992","journal-title":"Digital Tech J"},{"key":"ref81","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1970.7911"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/66.53188"},{"key":"ref84","first-page":"61","article-title":"yield, economic, and logistic models for complex digital arrays","author":"seeds","year":"0","journal-title":"1967 IEEE Int Conv Rec"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/66.210661"},{"key":"ref83","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-6799-8_11"},{"key":"ref19","doi-asserted-by":"crossref","author":"director","year":"1990","journal-title":"VLSI Design for Manufacturing Yield Enhancement","DOI":"10.1007\/978-1-4613-1521-6"},{"key":"ref80","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1981.1051533"},{"key":"ref89","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1975.1050655"},{"key":"ref85","first-page":"12","article-title":"yield and cost analysis of bipolar lsi","author":"seeds","year":"1967","journal-title":"1967 International Electron Devices Meeting"},{"key":"ref86","doi-asserted-by":"publisher","DOI":"10.1109\/12.8705"},{"key":"ref87","author":"spence","year":"1988","journal-title":"Tolerance Design of Electronic Circuits"},{"key":"ref88","doi-asserted-by":"publisher","DOI":"10.1109\/T-ED.1973.17719"}],"container-title":["Proceedings of the IEEE"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx4\/5\/15249\/00705525.pdf?arnumber=705525","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:08:14Z","timestamp":1638216494000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/705525\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998]]},"references-count":109,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/5.705525","relation":{},"ISSN":["0018-9219"],"issn-type":[{"value":"0018-9219","type":"print"}],"subject":[],"published":{"date-parts":[[1998]]}}}
