iBet uBet web content aggregator. Adding the entire web to your favor.
iBet uBet web content aggregator. Adding the entire web to your favor.



Link to original content: https://api.crossref.org/works/10.1109/43.863641
{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,23]],"date-time":"2024-09-23T03:39:28Z","timestamp":1727062768006},"reference-count":31,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2000]]},"DOI":"10.1109\/43.863641","type":"journal-article","created":{"date-parts":[[2002,8,24]],"date-time":"2002-08-24T17:57:42Z","timestamp":1030211862000},"page":"1011-1022","source":"Crossref","is-referenced-by-count":67,"title":["Generating synthetic benchmark circuits for evaluating CAD tools"],"prefix":"10.1109","volume":"19","author":[{"given":"D.","family":"Stroobandt","sequence":"first","affiliation":[]},{"given":"P.","family":"Verplaetse","sequence":"additional","affiliation":[]},{"given":"J.","family":"van Campenhout","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/43.273754"},{"key":"ref30","author":"sentovich","year":"1992","journal-title":"SIS A System for Sequential Circuit Analysis"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/43.728919"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/258305.258333"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/299996.300026"},{"key":"ref13","author":"stroobandt","year":"1998","journal-title":"Analytical Methods for a priori Wire Length Estimates in Computer systems"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1971.223159"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"66","DOI":"10.1109\/FPGA.1996.242345","article-title":"a method for generation random circuits and its application to routability measurement","author":"darnauer","year":"1996","journal-title":"Fourth International ACM Symposium on Field-Programmable Gate Arrays"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1999.780145"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1972.5008919"},{"key":"ref18","first-page":"136","article-title":"toward an extension of rent's rule for describing local variations in interconnection complexity","author":"van marck","year":"1995","journal-title":"Proc 4th Int Conf Young Computer Scientists"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1016\/S0141-9331(97)00023-9"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/299996.300030"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/S0167-9260(99)00002-4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2000.858726"},{"key":"ref27","first-page":"319","article-title":"a stochastic model for interconnection complexity based on rent's rule","author":"verplaetse","year":"2000","journal-title":"Proc IEEE Int Workshop Logic Synthesis"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"430","DOI":"10.1145\/196244.196452","article-title":"random generation of test instances for logic optimizers","author":"iwama","year":"1994","journal-title":"31st Design Automation Conference"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1016\/0167-9260(95)00008-4"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/43.87601"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.1998.655928"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/EDTC.1997.582338"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/274535.274546"},{"key":"ref1","article-title":"computer-aided design benchmarking laboratory","year":"0"},{"key":"ref9","doi-asserted-by":"crossref","author":"harlow iii","year":"1997","journal-title":"Synthesis of ESI equivalence class combinational circuit mutants","DOI":"10.21236\/ADA344593"},{"key":"ref20","first-page":"1024","article-title":"estimating interconnection lengths in three-dimensional computer systems","volume":"e80 d","author":"stroobandt","year":"1997","journal-title":"IEICE Trans Inform Syst"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/GLSV.1999.757445"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/2944.778313"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/GLSV.1998.665303"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/5.52212"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1982.1585498"},{"key":"ref25","author":"karypis","year":"1998","journal-title":"hMetis A Hypergraph Partitioning Package"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/18708\/00863641.pdf?arnumber=863641","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:07:36Z","timestamp":1638216456000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/863641\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000]]},"references-count":31,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/43.863641","relation":{},"ISSN":["0278-0070"],"issn-type":[{"value":"0278-0070","type":"print"}],"subject":[],"published":{"date-parts":[[2000]]}}}