{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,9,13]],"date-time":"2023-09-13T17:44:13Z","timestamp":1694627053483},"reference-count":10,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[1989,1,1]],"date-time":"1989-01-01T00:00:00Z","timestamp":599616000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[1989]]},"DOI":"10.1109\/4.34066","type":"journal-article","created":{"date-parts":[[2002,8,24]],"date-time":"2002-08-24T20:00:39Z","timestamp":1030219239000},"page":"889-894","source":"Crossref","is-referenced-by-count":11,"title":["New DRAM noise generation under half-V\/sub cc\/ precharge and its reduction using a transposed amplifier"],"prefix":"10.1109","volume":"24","author":[{"given":"M.","family":"Aoki","sequence":"first","affiliation":[]},{"given":"S.","family":"Ikenaga","sequence":"additional","affiliation":[]},{"given":"Y.","family":"Nakagome","sequence":"additional","affiliation":[]},{"given":"M.","family":"Horiguchi","sequence":"additional","affiliation":[]},{"given":"Y.","family":"Kawase","sequence":"additional","affiliation":[]},{"given":"Y.","family":"Kawamoto","sequence":"additional","affiliation":[]},{"given":"K.","family":"Itoh","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/16.2545"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/4.5932"},{"key":"ref10","article-title":"New DRAM noise generation under half VCC<\/subscript> precharge and its reduction using a transposed amplifier","author":"ikenega","year":"1988","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/4.5933"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/16.7358"},{"key":"ref8","first-page":"1","article-title":"3-D capacitance simulation of DRAM data line and its application to data line coupling noise evaluation","author":"ikenaga","year":"1987","journal-title":"Conf IEICE Japan Conf Rec"},{"key":"ref7","first-page":"66","article-title":"scaled bit line capacitance analysis using a three-dimensional simulator","author":"yoshida","year":"1985","journal-title":"1985 Symposium on VLSI Technology Digest of Technical Papers VLSIT"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/4.5931"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1988.663708"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1987.1157158"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx1\/4\/1419\/00034066.pdf?arnumber=34066","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:06:47Z","timestamp":1638216407000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/34066\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1989]]},"references-count":10,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/4.34066","relation":{},"ISSN":["0018-9200"],"issn-type":[{"value":"0018-9200","type":"print"}],"subject":[],"published":{"date-parts":[[1989]]}}}
