{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,5,11]],"date-time":"2022-05-11T05:25:51Z","timestamp":1652246751926},"reference-count":30,"publisher":"Institution of Engineering and Technology (IET)","issue":"4","license":[{"start":{"date-parts":[[2014,7,1]],"date-time":"2014-07-01T00:00:00Z","timestamp":1404172800000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"},{"start":{"date-parts":[[2014,7,1]],"date-time":"2014-07-01T00:00:00Z","timestamp":1404172800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/doi.wiley.com\/10.1002\/tdm_license_1.1"}],"funder":[{"DOI":"10.13039\/100005186","name":"Corporation for National and Community Service","doi-asserted-by":"publisher","award":["PN\u2010II\u2010RU\u2010TE\u20102011\u20103\u20100186"],"id":[{"id":"10.13039\/100005186","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IET Computers & Digital Techniques"],"published-print":{"date-parts":[[2014,7]]},"DOI":"10.1049\/iet-cdt.2013.0128","type":"journal-article","created":{"date-parts":[[2014,6,25]],"date-time":"2014-06-25T18:03:01Z","timestamp":1403719381000},"page":"187-197","source":"Crossref","is-referenced-by-count":5,"title":["Low\u2010precision DSP\u2010based floating\u2010point multiply\u2010add fused for Field Programmable Gate Arrays"],"prefix":"10.1049","volume":"8","author":[{"given":"Alexandru","family":"Amaricai","sequence":"first","affiliation":[{"name":"Computer Engineering DepartmentUniversity Politehnica of TimisoaraVasile Parvan Blvd., Nr. 2TimisoaraRomania"}]},{"given":"Oana","family":"Boncalo","sequence":"additional","affiliation":[{"name":"Computer Engineering DepartmentUniversity Politehnica of TimisoaraVasile Parvan Blvd., Nr. 2TimisoaraRomania"}]},{"given":"Constantina\u2010Elena","family":"Gavriliu","sequence":"additional","affiliation":[{"name":"Computer Engineering DepartmentUniversity Politehnica of TimisoaraVasile Parvan Blvd., Nr. 2TimisoaraRomania"}]}],"member":"265","published-online":{"date-parts":[[2014,7]]},"reference":[{"key":"e_1_2_7_2_2","doi-asserted-by":"crossref","unstructured":"Bensaali F. Amira A. Sotudeh R.: \u2018Floating\u2010point matrix product on FPGA\u2019.Proc. IEEE\/ACS Int. Conf. Computer Systems and Applications 2007 pp.466\u2013473","DOI":"10.1109\/AICCSA.2007.370923"},{"issue":"6","key":"e_1_2_7_3_2","doi-asserted-by":"crossref","first-page":"725","DOI":"10.1016\/j.micpro.2012.06.003","article-title":"A high performance, area efficient TTA\u2010like vertex shader architecture with optimized floating point arithmetic unit for embedded graphics applications","volume":"37","author":"Chang Y.","year":"2013","journal-title":"Microprocessors Microsyst."},{"key":"e_1_2_7_4_2","doi-asserted-by":"crossref","unstructured":"Dou Y. Vassiliadis S. Kuzmanov G.K. Gaydadijev G.N.: \u201864\u2010bit floating\u2010point FPGA matrix multiplication\u2019.Proc. ACM\/SIGDA 13th Int. Symp. On Field Programmable Gate Arrays (FPGA) 2005 pp.86\u201395","DOI":"10.1145\/1046192.1046204"},{"key":"e_1_2_7_5_2","doi-asserted-by":"crossref","unstructured":"Holanda B. Pimentel R. Barbosa J. et al.: \u2018An FPGA\u2010based accelerator to speed\u2010up matrix multiplication of floating point operations\u2019.Proc. 2011 IEEE Int. Symp. on Parallel and Distributed Processing Workshops and PhD Forum 2011 pp.306\u2013309","DOI":"10.1109\/IPDPS.2011.165"},{"issue":"4","key":"e_1_2_7_6_2","doi-asserted-by":"crossref","first-page":"249","DOI":"10.1049\/iet-cdt.2011.0132","article-title":"FPGA accelerator for floating\u2010point matrix multiplication","volume":"6","author":"Jovanovic Z.","year":"2012","journal-title":"IET Comput. Digital Tech."},{"key":"e_1_2_7_7_2","unstructured":"Bruguera J.D. Lang T.: \u2018Floating\u2010point fused multiply\u2010add: reduced latency for floating\u2010point addition\u2019.Proc. 17th IEEE Symp. On Computer Arithmetic (ARITH) 2005 pp.42\u201351"},{"key":"e_1_2_7_8_2","volume-title":"Handbook of floating point arithmetic","author":"Muller J.M.","year":"2009"},{"issue":"12","key":"e_1_2_7_9_2","doi-asserted-by":"crossref","first-page":"1727","DOI":"10.1109\/TVLSI.2008.2001944","article-title":"Bridge floating\u2010point fused multiply\u2010add design","volume":"16","author":"Quinnell E.","year":"2008","journal-title":"IEEE Trans. VLSI Syst."},{"key":"e_1_2_7_10_2","unstructured":"Lang T. Bruguera J.D.: \u2018Floating\u2010point fused multiply\u2010add with reduced latency\u2019.Proc. 2002 IEEE Int. Conf. Computer Design (ICCD) 2002 pp.145\u2013150"},{"key":"e_1_2_7_11_2","unstructured":"Xilinx \u2013 \u2018Xilinx LogiCORE Floating Point Operator v6.2\u2019 \u2013 Product Guide 2012"},{"key":"e_1_2_7_12_2","unstructured":"Xilinx \u2013 \u2018Virtex\u20105 FPGA XtremeDSP Design Considerations\u2019 \u2013 User Guide 2012"},{"issue":"1","key":"e_1_2_7_13_2","doi-asserted-by":"crossref","first-page":"30","DOI":"10.1016\/j.mejo.2007.11.001","article-title":"Multi\u2010functional floating\u2010point MAF designs with dot product support","volume":"39","author":"Gok M.","year":"2008","journal-title":"Microelectron. J."},{"key":"e_1_2_7_14_2","first-page":"284","article-title":"Low power floating point MAFs \u2013 a comparative study","volume":"1","author":"Pillai R.V.K.","year":"2001","journal-title":"Proc. Sixth Int. Symp. Signal Processing and its Applications"},{"key":"e_1_2_7_15_2","doi-asserted-by":"crossref","unstructured":"Preiss J. Boersma M. M\u00fcller S.: \u2018Advanced clockgating schemes for fused\u2010multiply\u2010add\u2010type floating\u2010point units\u2019.Proc. 19th IEEE Symp. On Computer Arithmetic 2009 pp.48\u201356","DOI":"10.1109\/ARITH.2009.17"},{"key":"e_1_2_7_16_2","unstructured":"Seidel P.\u2010M.: \u2018Multiple path IEEE floating\u2010point fused multiply\u2010add\u2019.Proc. 46th IEEE Int. Midwest Symp. on Circuits and Systems 2003 pp.1359\u20131362"},{"key":"e_1_2_7_17_2","unstructured":"Xiao\u2010Lu M.: \u2018Leading zero anticipation for latency improvement in floating\u2010point fused multiply\u2010add units\u2019.Proc. Sixth Int. Conf. ASIC 2005 pp.53\u201356"},{"key":"e_1_2_7_18_2","doi-asserted-by":"crossref","unstructured":"deLorimier M. DeHon M.: \u2018Floating\u2010point sparse matrix\u2010vector multiply for FPGAs\u2019.Proc. ACM\/SIGDA 13th Int. Symp. on Field Programmable Gate Arrays (FPGA) 2005 pp.75\u201385","DOI":"10.1145\/1046192.1046203"},{"issue":"5","key":"e_1_2_7_19_2","doi-asserted-by":"crossref","first-page":"421","DOI":"10.1016\/j.mejo.2013.02.021","article-title":"Area\u2010efficient architectures for double precision multiplier on FPGA, with run\u2010time\u2010reconfigurable dual single precision support","volume":"44","author":"Jaiswal M.K.","year":"2013","journal-title":"Microelectron. J."},{"issue":"2","key":"e_1_2_7_20_2","doi-asserted-by":"crossref","first-page":"580","DOI":"10.1007\/s11227-012-0860-0","article-title":"FPGA implementation of an exact dot product and its application in variable\u2010precision floating\u2010point arithmetic","volume":"64","author":"Lei Y.","year":"2013","journal-title":"J. Supercomput."},{"key":"e_1_2_7_21_2","doi-asserted-by":"crossref","unstructured":"Sun S. Zambreno J.: \u2018A floating\u2010point accumulator for FPGA\u2010based high performance computing applications\u2019.Proc. 2009 Int. Conf. Field Programmable Technology (FPT) 2009 pp.493\u2013499","DOI":"10.1109\/FPT.2009.5377624"},{"issue":"4","key":"e_1_2_7_22_2","doi-asserted-by":"crossref","first-page":"18","DOI":"10.1109\/MDT.2011.44","article-title":"Designing custom arithmetic data paths with FloPoCo","volume":"28","author":"Dinechin de F.","year":"2011","journal-title":"IEEE Design Test Comput."},{"key":"e_1_2_7_23_2","doi-asserted-by":"crossref","unstructured":"Dinechin de F. Pasca B. Cret O. Tudoran R.: \u2018An FPGA\u2010specific approach to floating\u2010point accumulation and sum\u2010of\u2010products\u2019.Proc. 2008 Int. Conf. Field Programmable Technology (FPT) 2008 pp.33\u201340","DOI":"10.1109\/FPT.2008.4762363"},{"key":"e_1_2_7_24_2","doi-asserted-by":"crossref","unstructured":"Lopes A.R. Constantinides G.: \u2018A fused hybrid floating\u2010point and fixed\u2010point dot\u2010product for FPGAs\u2019.Proc. Sixth Int. Conf. Reconfigurable Computing: Architectures Tools and Applications (ARC'10) 2010 pp.157\u2013168","DOI":"10.1007\/978-3-642-12133-3_16"},{"key":"e_1_2_7_25_2","doi-asserted-by":"crossref","unstructured":"Paidimari A. Cevrero A. Brisk P. Ienne P.: \u2018FPGA implementation of a single\u2010precision floating\u2010point multiply\u2010accumulator with single\u2010cycle accumulation\u2019.Proc. 17th IEEE Symp. Field Programmable Custom Computing Machines (FCCM) 2009 pp.267\u2013270","DOI":"10.1109\/FCCM.2009.50"},{"issue":"8","key":"e_1_2_7_26_2","doi-asserted-by":"crossref","first-page":"606","DOI":"10.1016\/j.micpro.2012.06.009","article-title":"FPGA\u2010specific synthesis of loop\u2010nests with pipelined computational cores","volume":"36","author":"Alias C.","year":"2012","journal-title":"Microprocess. Microsyst."},{"issue":"1","key":"e_1_2_7_27_2","doi-asserted-by":"crossref","first-page":"124","DOI":"10.1109\/92.273153","article-title":"An algorithmic and novel design of a leading zero detector circuit: Comparison with logic synthesis","volume":"2","author":"Oklobdzija V.G.","year":"1994","journal-title":"IEEE Trans. VLSI Syst."},{"issue":"3","key":"e_1_2_7_28_2","article-title":"Fast, efficient floating\u2010point adders and multipliers for FPGAs","volume":"3","author":"Hemmert K.S.","year":"2010","journal-title":"ACM. Trans. Reconfigurable Technol. Syst. (TRETS)"},{"issue":"4","key":"e_1_2_7_29_2","doi-asserted-by":"crossref","first-page":"305","DOI":"10.1049\/iet-cdt:20070075","article-title":"High\u2010performance, low\u2010latency field\u2010programmable gate array\u2010based floating\u2010point adder and multiplier units in a Virtex 4","volume":"2","author":"Karlstrom P.","year":"2008","journal-title":"IET Comput. Digital Tech."},{"issue":"6","key":"e_1_2_7_30_2","doi-asserted-by":"crossref","first-page":"535","DOI":"10.1016\/j.micpro.2011.04.004","article-title":"Customizing floating\u2010point units for FPGAs: area\u2010performance\u2010standard trade\u2010offs","volume":"35","author":"Echeverria P.","year":"2011","journal-title":"Microprocess. Microsyst."},{"key":"e_1_2_7_31_2","doi-asserted-by":"crossref","unstructured":"Langhammer M. VanCourt T.: \u2018FPGA floating point datapath compiler\u2019.Proc. 17th IEEE Symp. on Field Programmable Custom Computing Machines (FCCM) 2009 pp.259\u2013262","DOI":"10.1109\/FCCM.2009.54"}],"container-title":["IET Computers & Digital Techniques"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1049\/iet-cdt.2013.0128","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/full-xml\/10.1049\/iet-cdt.2013.0128","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1049\/iet-cdt.2013.0128","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,2,5]],"date-time":"2021-02-05T23:03:13Z","timestamp":1612566193000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1049\/iet-cdt.2013.0128"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,7]]},"references-count":30,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2014,7]]}},"alternative-id":["10.1049\/iet-cdt.2013.0128"],"URL":"https:\/\/doi.org\/10.1049\/iet-cdt.2013.0128","archive":["Portico"],"relation":{},"ISSN":["1751-8601","1751-861X"],"issn-type":[{"value":"1751-8601","type":"print"},{"value":"1751-861X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,7]]}}}
