{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,9,13]],"date-time":"2023-09-13T20:33:58Z","timestamp":1694637238837},"reference-count":14,"publisher":"Elsevier BV","issue":"10-12","license":[{"start":{"date-parts":[[2009,10,1]],"date-time":"2009-10-01T00:00:00Z","timestamp":1254355200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Systems Architecture"],"published-print":{"date-parts":[[2009,10]]},"DOI":"10.1016\/j.sysarc.2009.09.003","type":"journal-article","created":{"date-parts":[[2009,9,19]],"date-time":"2009-09-19T09:21:58Z","timestamp":1253352118000},"page":"446-456","source":"Crossref","is-referenced-by-count":1,"title":["Reusability-aware cache memory sharing for chip multiprocessors with private L2 caches"],"prefix":"10.1016","volume":"55","author":[{"given":"Hyunhee","family":"Kim","sequence":"first","affiliation":[]},{"given":"Sungjun","family":"Youn","sequence":"additional","affiliation":[]},{"given":"Jihong","family":"Kim","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/j.sysarc.2009.09.003_bib1","unstructured":"J. Huh, D. Burger, S.W. Keckler, Exploring the design space of future CMPs, in: Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, September 2001, pp. 199\u2013210."},{"key":"10.1016\/j.sysarc.2009.09.003_bib2","doi-asserted-by":"crossref","unstructured":"B.A. Nayfeh, L. Hammond, K. Olukotun, Evaluation of design alternatives for a multiprocessor microprocessor, in: Proceedings of the International Symposium on Computer Architecture, May 1996, pp. 67\u201377.","DOI":"10.1145\/232974.232982"},{"key":"10.1016\/j.sysarc.2009.09.003_bib3","unstructured":"B.M. Beckmann, D.A. Wood, Managing wire delay in large chip-multiprocessor cache, in: Proceedings of the International Symposium on Microarchitecture, December 2004, pp. 319\u2013330."},{"key":"10.1016\/j.sysarc.2009.09.003_bib4","doi-asserted-by":"crossref","unstructured":"M. Zhang, K. Asanovic, Victim replication: maximizing capacity while hiding wire delay in tiled chip multiprocessors, in: Proceedings of the International Symposium on Computer Architecture, June 2005, pp. 336\u2013345.","DOI":"10.1145\/1080695.1069998"},{"key":"10.1016\/j.sysarc.2009.09.003_bib5","doi-asserted-by":"crossref","unstructured":"Z. Chishti, M.D. Powell, T.N. Vijaykumar, Optimizing replication, communication and capacity allocation in CMPs, in: Proceedings of the International Symposium on Computer Architecture, June 2005, pp. 357\u2013368.","DOI":"10.1145\/1080695.1070001"},{"key":"10.1016\/j.sysarc.2009.09.003_bib6","unstructured":"J. Chang, G.S. Sohi, Cooperative caching for chip multiprocessors, in: Proceedings of the International Symposium on Computer Architecture, June 2006, pp. 357\u2013368."},{"key":"10.1016\/j.sysarc.2009.09.003_bib7","doi-asserted-by":"crossref","unstructured":"S. Youn, H. Kim, J. Kim, A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 Caches, in: Proceedings of International Symposium on Low Power Electronics and Design, August 2007, pp. 56\u201361.","DOI":"10.1145\/1283780.1283793"},{"key":"10.1016\/j.sysarc.2009.09.003_bib8","doi-asserted-by":"crossref","unstructured":"S. Youn, H. Kim, J. Kim, A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 caches, in: Proceedings of the Workshop on Chip Multiprocessor Memory Systems and Interconnects, February 2007, pp. 27\u201332.","DOI":"10.1145\/1283780.1283793"},{"key":"10.1016\/j.sysarc.2009.09.003_bib9","doi-asserted-by":"crossref","unstructured":"C. Kim, D. Burger, S.W. Keckler, An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches, in: Proceedings of the Architectural Support for Programming Languages and Operating Systems, October 2002, pp. 211\u2013222.","DOI":"10.1145\/635508.605420"},{"key":"10.1016\/j.sysarc.2009.09.003_bib10","doi-asserted-by":"crossref","unstructured":"E. Speight, H. Shafi, L. Zhang, R. Rajamony, Adaptive mechanisms and policies for managing cache hierarchies in chip multiprocessors, in: Proceedings of the International Symposium on Computer Architecture, June 2005, pp. 346\u2013356.","DOI":"10.1145\/1080695.1069999"},{"issue":"12","key":"10.1016\/j.sysarc.2009.09.003_bib11","doi-asserted-by":"crossref","first-page":"1352","DOI":"10.1109\/TC.2001.970573","article-title":"LRFU: a spectrum of policies that subsumes the least recently used and least frequently used policies","volume":"50","author":"Lee","year":"2001","journal-title":"IEEE Transactions on Computers"},{"key":"10.1016\/j.sysarc.2009.09.003_bib12","doi-asserted-by":"crossref","unstructured":"D. Kim, S. Ha, R. Gupta, CATS: cycle accurate transaction-driven simulation with multiple processor simulators, in: Proceedings of the Design, Automation, and Test in Europe, April 2007, pp. 749\u2013754.","DOI":"10.1109\/DATE.2007.364685"},{"key":"10.1016\/j.sysarc.2009.09.003_bib13","doi-asserted-by":"crossref","unstructured":"S.C. Woo, M. Ohara, E. Torrie, J.P. Singh, A. Gupta, The SPLASH-2 programs: characterization and methodological considerations, in: Proceedings of the International Symposium on Computer Architecture, June 1995, pp. 24\u201336.","DOI":"10.1145\/225830.223990"},{"key":"10.1016\/j.sysarc.2009.09.003_bib14","series-title":"Parallel Computer Architecture: A Hardware\/Software Approach","isbn-type":"print","author":"Culler","year":"1998","ISBN":"http:\/\/id.crossref.org\/isbn\/1558603433"}],"container-title":["Journal of Systems Architecture"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762109000599?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762109000599?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2022,7,11]],"date-time":"2022-07-11T06:09:23Z","timestamp":1657519763000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S1383762109000599"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,10]]},"references-count":14,"journal-issue":{"issue":"10-12","published-print":{"date-parts":[[2009,10]]}},"alternative-id":["S1383762109000599"],"URL":"http:\/\/dx.doi.org\/10.1016\/j.sysarc.2009.09.003","relation":{},"ISSN":["1383-7621"],"issn-type":[{"value":"1383-7621","type":"print"}],"subject":[],"published":{"date-parts":[[2009,10]]}}}