{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,7,5]],"date-time":"2024-07-05T00:14:46Z","timestamp":1720138486567},"reference-count":52,"publisher":"Elsevier","license":[{"start":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T00:00:00Z","timestamp":1514764800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018]]},"DOI":"10.1016\/bs.adcom.2018.04.002","type":"book-chapter","created":{"date-parts":[[2018,6,19]],"date-time":"2018-06-19T02:44:58Z","timestamp":1529376298000},"page":"259-294","source":"Crossref","is-referenced-by-count":7,"title":["Introduction to Emerging SRAM-Based FPGA Architectures in Dark Silicon Era"],"prefix":"10.1016","author":[{"given":"Zeinab","family":"Seifoori","sequence":"first","affiliation":[]},{"given":"Zahra","family":"Ebrahimi","sequence":"additional","affiliation":[]},{"given":"Behnam","family":"Khaleghi","sequence":"additional","affiliation":[]},{"given":"Hossein","family":"Asadi","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"issue":"2","key":"10.1016\/bs.adcom.2018.04.002_bb0010","doi-asserted-by":"crossref","first-page":"203","DOI":"10.1109\/TCAD.2006.884574","article-title":"Measuring the gap between FPGAs and ASICs","volume":"26","author":"Kuon","year":"2007","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"issue":"4","key":"10.1016\/bs.adcom.2018.04.002_bb0015","doi-asserted-by":"crossref","first-page":"6","DOI":"10.1109\/MM.2011.77","article-title":"Toward dark silicon in servers","volume":"31","author":"Hardavellas","year":"2011","journal-title":"IEEE Micro."},{"issue":"1","key":"10.1016\/bs.adcom.2018.04.002_bb0020","doi-asserted-by":"crossref","first-page":"205","DOI":"10.1145\/1735970.1736044","article-title":"Conservation cores: reducing the energy of mature computations","volume":"38","author":"Venkatesh","year":"2010","journal-title":"ACM SIGARCH Comput. Archit. News"},{"key":"10.1016\/bs.adcom.2018.04.002_bb0025","series-title":"COFFE: fully-automated transistor sizing for FPGAs","author":"Chiasson","year":"2013"},{"issue":"3","key":"10.1016\/bs.adcom.2018.04.002_bb0030","doi-asserted-by":"crossref","first-page":"288","DOI":"10.1109\/TVLSI.2004.824300","article-title":"The effect of LUT and cluster size on deep-submicron FPGA performance and density","volume":"12","author":"Ahmed","year":"2004","journal-title":"IEEE Trans. Very Large Scale Integr. VLSI Syst."},{"key":"10.1016\/bs.adcom.2018.04.002_bb0035","series-title":"The Design Warrior's Guide to FPGAs: Devices, Tools and Flows","author":"Maxfield","year":"2004"},{"key":"10.1016\/bs.adcom.2018.04.002_bb0040","series-title":"Proceedings of the 2015 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays","article-title":"Impact of memory architecture on FPGA energy consumption","author":"Kadric","year":"2015"},{"issue":"6","key":"10.1016\/bs.adcom.2018.04.002_bb0045","doi-asserted-by":"crossref","first-page":"982","DOI":"10.1109\/TC.2016.2636141","article-title":"PEAF: a power-efficient architecture for SRAM-based FPGAs using reconfigurable hard logic design in dark silicon era","volume":"66","author":"Ebrahimi","year":"2017","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/bs.adcom.2018.04.002_bb0050","series-title":"ASME 2016 5th International Conference on Micro\/Nanoscale Heat and Mass Transfer","article-title":"Unit cell model formulation and thermal performance analysis for cross-flow heat exchanger","author":"Zhang","year":"2016"},{"key":"10.1016\/bs.adcom.2018.04.002_bb0055","series-title":"Power and Programmability: The Challenges of Exascale Computing","author":"Dally","year":"2012"},{"issue":"1","key":"10.1016\/bs.adcom.2018.04.002_bb0060","doi-asserted-by":"crossref","first-page":"178","DOI":"10.1109\/TVLSI.2015.2393914","article-title":"An FPGA architecture and CAD flow supporting dynamically controlled power gating","volume":"24","author":"Bsoul","year":"2016","journal-title":"IEEE Trans. Very Large Scale Integr. VLSI Syst."},{"key":"10.1016\/bs.adcom.2018.04.002_bb0065","series-title":"An FPGA architecture supporting dynamically controlled power gating","author":"Wilton","year":"2010"},{"key":"10.1016\/bs.adcom.2018.04.002_bb0070","series-title":"The Rise and Fall of Dark Silicon","author":"Hardavellas","year":"2012"},{"key":"10.1016\/bs.adcom.2018.04.002_bb0075","series-title":"A Perspective on Dark Silicon","author":"Kanduri","year":"2017"},{"issue":"5","key":"10.1016\/bs.adcom.2018.04.002_bb0080","doi-asserted-by":"crossref","first-page":"371","DOI":"10.1016\/S1359-0286(02)00116-X","article-title":"The international technology roadmap for semiconductors\u2014perspectives and challenges for the next 15 years","volume":"6","author":"Arden","year":"2002","journal-title":"Curr. Opin. Solid State Mater. Sci."},{"key":"10.1016\/bs.adcom.2018.04.002_bb0085","series-title":"The exascale challenge","author":"Borkar","year":"2010"},{"key":"10.1016\/bs.adcom.2018.04.002_bb0090","article-title":"The death of CPU scaling: from one core to many\u2014and why we\u2019re still stuck","author":"Hruska","year":"2012","journal-title":"ExtremeTech [online]"},{"issue":"3","key":"10.1016\/bs.adcom.2018.04.002_bb0095","doi-asserted-by":"crossref","first-page":"365","DOI":"10.1145\/2024723.2000108","article-title":"Dark silicon and the end of multicore scaling","volume":"39","author":"Esmaeilzadeh","year":"2011","journal-title":"ACM SIGARCH Comput. Archit. News"},{"key":"10.1016\/bs.adcom.2018.04.002_bb0100","series-title":"Is dark silicon useful? Harnessing the four horsemen of the coming dark silicon apocalypse","first-page":"1131","author":"Taylor","year":"2012"},{"key":"10.1016\/bs.adcom.2018.04.002_bb0105","series-title":"A 280mV-to-1.2 V wide-operating-range IA-32 processor in 32nm CMOS","author":"Shailendra","year":"2012"},{"issue":"1","key":"10.1016\/bs.adcom.2018.04.002_bb0110","doi-asserted-by":"crossref","first-page":"21","DOI":"10.1109\/L-CA.2010.5","article-title":"Synctium: a near-threshold stream processor for energy-constrained parallel applications","volume":"9","author":"Krimer","year":"2010","journal-title":"IEEE Comput. Archit. Lett."},{"key":"10.1016\/bs.adcom.2018.04.002_bb0115","first-page":"503","article-title":"Dynamically specialized datapaths for energy efficient computing","author":"Govindaraju","year":"2011"},{"key":"10.1016\/bs.adcom.2018.04.002_bb0120","series-title":"Designing for dark silicon: a methodological perspective on energy efficient systems","author":"Allred","year":"2012"},{"key":"10.1016\/bs.adcom.2018.04.002_bb0125","series-title":"Architecture support for accelerator-rich cmps","author":"Cong","year":"2012"},{"issue":"4","key":"10.1016\/bs.adcom.2018.04.002_bb0130","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2086696.2086727","article-title":"The accelerator store: a shared memory framework for accelerator-based systems","volume":"8","author":"Lyons","year":"2012","journal-title":"ACM Trans. Archit. Code Optim"},{"key":"10.1016\/bs.adcom.2018.04.002_bb0135","series-title":"Hades: architectural synthesis for heterogeneous dark silicon chip multi-processors","author":"Turakhia","year":"2013"},{"issue":"1","key":"10.1016\/bs.adcom.2018.04.002_bb0140","doi-asserted-by":"crossref","first-page":"308","DOI":"10.1109\/JSSC.2010.2074370","article-title":"Demonstration of integrated micro-electro-mechanical relay circuits for VLSI applications","volume":"46","author":"Spencer","year":"2011","journal-title":"IEEE J. Solid State Circuits"},{"key":"10.1016\/bs.adcom.2018.04.002_bb0145","first-page":"306","article-title":"Design and analysis of hybrid NEMS-CMOS circuits for ultra low-power applications","author":"Dadgour","year":"2007"},{"issue":"7373","key":"10.1016\/bs.adcom.2018.04.002_bb0150","doi-asserted-by":"crossref","first-page":"329","DOI":"10.1038\/nature10679","article-title":"Tunnel field-effect transistors as energy-efficient electronic switches","volume":"479","author":"Ionescu","year":"2011","journal-title":"Nature"},{"key":"10.1016\/bs.adcom.2018.04.002_bb0155","series-title":"Reliable on-chip systems in the nano-era: lessons learnt and future trends","author":"Henkel","year":"2013"},{"key":"10.1016\/bs.adcom.2018.04.002_bb0160","series-title":"Multi-layer dependability: from microarchitecture to application level","author":"Henkel","year":"2014"},{"key":"10.1016\/bs.adcom.2018.04.002_bb0165","series-title":"Aser: adaptive soft error resilience for reliability-heterogeneous processors in the dark silicon era","author":"Kriebel","year":"2014"},{"key":"10.1016\/bs.adcom.2018.04.002_bb0170","series-title":"Cherry-picking: exploiting process variations in dark-silicon homogeneous chip multi-processors","author":"Raghunathan","year":"2013"},{"key":"10.1016\/bs.adcom.2018.04.002_bb0175","series-title":"The EDA challenges in the dark silicon era: temperature, reliability, and variability perspectives","author":"Shafique","year":"2014"},{"key":"10.1016\/bs.adcom.2018.04.002_bb0180","series-title":"Towards dark silicon era in fpgas using complementary hard logic design","author":"Ahari","year":"2014"},{"issue":"8","key":"10.1016\/bs.adcom.2018.04.002_bb0185","doi-asserted-by":"crossref","first-page":"1394","DOI":"10.1109\/TVLSI.2010.2050500","article-title":"A low-power FPGA based on autonomous fine-grain power gating","volume":"19","author":"Ishihara","year":"2011","journal-title":"IEEE Trans. Very Large Scale Integr. VLSI Syst."},{"key":"10.1016\/bs.adcom.2018.04.002_bb0190","series-title":"High-level synthesis-based design methodology for Dynamic Power-Gated FPGAs","author":"Ahmed","year":"2014"},{"issue":"8","key":"10.1016\/bs.adcom.2018.04.002_bb0195","doi-asserted-by":"crossref","first-page":"1048","DOI":"10.1109\/TVLSI.2009.2017443","article-title":"Low-power programmable FPGA routing circuitry","volume":"17","author":"Anderson","year":"2009","journal-title":"IEEE Trans. Very Large Scale Integr. VLSI Syst."},{"key":"10.1016\/bs.adcom.2018.04.002_bb0200","series-title":"Low energy switch block for FPGAs","author":"Krishnan","year":"2004"},{"key":"10.1016\/bs.adcom.2018.04.002_bb0205","series-title":"Power Consumption at 40 and 45 nm","author":"Klein","year":"2009"},{"issue":"3","key":"10.1016\/bs.adcom.2018.04.002_bb0210","doi-asserted-by":"crossref","first-page":"423","DOI":"10.1109\/TCAD.2005.853692","article-title":"Active leakage power optimization for FPGAs","volume":"25","author":"Anderson","year":"2006","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"key":"10.1016\/bs.adcom.2018.04.002_bb0215","series-title":"Leakage control in FPGA routing fabric","author":"Srinivasan","year":"2005"},{"key":"10.1016\/bs.adcom.2018.04.002_bb0220","series-title":"Leakage reduction in FPGA routing multiplexers","author":"Hasan","year":"2009"},{"key":"10.1016\/bs.adcom.2018.04.002_bb0225","series-title":"An FPGA architecture supporting dynamically controlled power gating","author":"Bsoul","year":"2010"},{"key":"10.1016\/bs.adcom.2018.04.002_bb0230","series-title":"Exploiting temporal idleness to reduce leakage power in programmable architectures","author":"Bharadwaj","year":"2005"},{"key":"10.1016\/bs.adcom.2018.04.002_bb0235","series-title":"Reducing leakage energy in FPGAs using region-constrained placement","author":"Gayasen","year":"2004"},{"key":"10.1016\/bs.adcom.2018.04.002_bb0240","series-title":"New power-aware placement for region-based FPGA architecture combined with dynamic power gating by PCHM","author":"Li","year":"2011"},{"key":"10.1016\/bs.adcom.2018.04.002_bb0245","series-title":"An FPGA with power-gated switch blocks","author":"Bsoul","year":"2012"},{"issue":"10","key":"10.1016\/bs.adcom.2018.04.002_bb0250","doi-asserted-by":"crossref","first-page":"798","DOI":"10.1109\/TCSII.2014.2345291","article-title":"Fine-grained architecture in dark silicon era for SRAM-based reconfigurable devices","volume":"61","author":"Yazdanshenas","year":"2014","journal-title":"IEEE Trans. Circuits Syst. Express Briefs"},{"key":"10.1016\/bs.adcom.2018.04.002_bb0255","series-title":"A directional coarse-grained power gated FPGA switch box and power gating aware routing algorithm","author":"Hoo","year":"2013"},{"key":"10.1016\/bs.adcom.2018.04.002_bb0260","series-title":"Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction","author":"Lin","year":"2005"},{"key":"10.1016\/bs.adcom.2018.04.002_bb0265","series-title":"A Power gating switch box architecture in routing network of SRAM-based FPGAs in dark silicon era","author":"Seifoori","year":"2017"}],"container-title":["Advances in Computers","Dark Silicon and Future On-chip Systems"],"original-title":[],"link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0065245818300421?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0065245818300421?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2018,7,26]],"date-time":"2018-07-26T08:52:21Z","timestamp":1532595141000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0065245818300421"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018]]},"references-count":52,"URL":"http:\/\/dx.doi.org\/10.1016\/bs.adcom.2018.04.002","relation":{},"ISSN":["0065-2458"],"issn-type":[{"value":"0065-2458","type":"print"}],"subject":[],"published":{"date-parts":[[2018]]}}}
