{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T13:54:52Z","timestamp":1725803692541},"publisher-location":"New Delhi","reference-count":23,"publisher":"Springer India","isbn-type":[{"type":"print","value":"9788132219873"},{"type":"electronic","value":"9788132219880"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015]]},"DOI":"10.1007\/978-81-322-1988-0_8","type":"book-chapter","created":{"date-parts":[[2014,8,26]],"date-time":"2014-08-26T04:45:57Z","timestamp":1409028357000},"page":"131-144","source":"Crossref","is-referenced-by-count":9,"title":["An ESOP-Based Reversible Circuit Synthesis Flow Using Simulated Annealing"],"prefix":"10.1007","author":[{"given":"Kamalika","family":"Datta","sequence":"first","affiliation":[]},{"given":"Alhaad","family":"Gokhale","sequence":"additional","affiliation":[]},{"given":"Indranil","family":"Sengupta","sequence":"additional","affiliation":[]},{"given":"Hafizur","family":"Rahaman","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2014,8,27]]},"reference":[{"issue":"5","key":"8_CR1","doi-asserted-by":"publisher","first-page":"3457","DOI":"10.1103\/PhysRevA.52.3457","volume":"52","author":"A Barenco","year":"1995","unstructured":"Barenco, A., Bennett, H.H., Cleve, R., DiVinchenzo, D.P., Margolus, N., Shor, P., Sleator, T., Smolin, J.A., Weinfurter, H.: Elementary gates for quantum computation. Phys. Rev. A (At. Mol. Opt. Phy.) 52(5), 3457\u20133467 (1995)","journal-title":"Phys. Rev. A (At. Mol. Opt. Phy.)"},{"key":"8_CR2","doi-asserted-by":"publisher","first-page":"525","DOI":"10.1147\/rd.176.0525","volume":"17","author":"CH Bennett","year":"1973","unstructured":"Bennett, C.H.: Logical reversibility of computation. J. IBM Res. Dev. 17, 525\u2013532 (1973)","journal-title":"J. IBM Res. Dev."},{"issue":"3","key":"8_CR3","doi-asserted-by":"publisher","first-page":"187","DOI":"10.1038\/nature10872","volume":"483","author":"A B\u00e8rut","year":"2012","unstructured":"B\u00e8rut, A., Arakelyan, A., Petrosyan, A., Ciliberto, S., Dillenschneider, R., Lutz, E.: Experimental verification of Landauer\u2019s principle linking information and thermodynamics. Nature 483(3), 187\u2013189 (2012)","journal-title":"Nature"},{"key":"8_CR4","doi-asserted-by":"crossref","unstructured":"Datta, K., Rathi, G., Sengupta, I., Rahaman, H.: Synthesis of reversible circuits using heuristic search method. In: Proceedings of 25th International Conference on VLSI Design, pp. 328\u2013333 (2012)","DOI":"10.1109\/VLSID.2012.92"},{"key":"8_CR5","doi-asserted-by":"crossref","unstructured":"Datta, K., Shrivastav, V., Sengupta, I., Rahaman, H.: Reversible logic implementation of AES algorithm. In: Proceedings of Design and Technology of Integrated Systems (DTIS), March 2013","DOI":"10.1109\/DTIS.2013.6527794"},{"key":"8_CR6","doi-asserted-by":"crossref","unstructured":"Drechsler, R., Finder, A., Wille, R.: Improving ESOP-based synthesis of reversible logic using evolutionary algorithms. In: Proceedings of International Conference on Applications of Evolutionary Computation (Part II), pp. 151\u2013161 (2011)","DOI":"10.1007\/978-3-642-20520-0_16"},{"key":"8_CR7","doi-asserted-by":"crossref","unstructured":"Fazel, K., Thornton, MA., Rice, J.: ESOP-based Toffoli gate cascade generation. In: Proceedings of IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, pp. 206\u2013209 (2007)","DOI":"10.1109\/PACRIM.2007.4313212"},{"key":"8_CR8","doi-asserted-by":"crossref","unstructured":"Finder, A., Drechsler, R.: An evolutionary algorithms for optimization of pseudo Kronecker expressions. In: Proceedings of International Symposium on Multi-Valued Logic, pp. 150\u2013155 (2010)","DOI":"10.1109\/ISMVL.2010.36"},{"issue":"5","key":"8_CR9","doi-asserted-by":"publisher","first-page":"703","DOI":"10.1109\/TCAD.2009.2017215","volume":"28","author":"D Grosse","year":"2009","unstructured":"Grosse, D., Wille, R., Dueck, G.W., Drechsler, R.: Exact multiple control Toffoli network synthesis with SAT techniques. IEEE Trans. CAD Integr. Circuits Syst. 28(5), 703\u2013715 (2009)","journal-title":"IEEE Trans. CAD Integr. Circuits Syst."},{"issue":"11","key":"8_CR10","doi-asserted-by":"publisher","first-page":"2317","DOI":"10.1109\/TCAD.2006.871622","volume":"25","author":"P Gupta","year":"2006","unstructured":"Gupta, P., Agrawal, A., Jha, N.K.: An algorithm for synthesis of reversible logic circuits. IEEE Trans. CAD Integr. Circuits Syst. 25(11), 2317\u20132329 (2006)","journal-title":"IEEE Trans. CAD Integr. Circuits Syst."},{"key":"8_CR11","doi-asserted-by":"publisher","first-page":"183","DOI":"10.1147\/rd.53.0183","volume":"5","author":"R Landauer","year":"1961","unstructured":"Landauer, R.: Irreversibility and heat generation in computing process. J. IBM Res. Dev. 5, 183\u2013191 (1961)","journal-title":"J. IBM Res. Dev."},{"issue":"3","key":"8_CR12","doi-asserted-by":"publisher","first-page":"436","DOI":"10.1109\/TCAD.2007.911334","volume":"27","author":"D Maslov","year":"2008","unstructured":"Maslov, D., Dueck, G.W.: Quantum circuit simplification and level compaction. IEEE Trans. CAD Integr. Circuits Syst. 27(3), 436\u2013444 (2008)","journal-title":"IEEE Trans. CAD Integr. Circuits Syst."},{"key":"8_CR13","unstructured":"Mishchenko, A., Perkowski, M.: Fast heuristic minimization of exclusive-sums-of-products. In: Proceedings of 6th Reed-Muller Workshop, pp. 242\u2013250 (2001)"},{"issue":"8","key":"8_CR14","first-page":"183","volume":"38","author":"GE Moore","year":"1965","unstructured":"Moore, G.E.: Cramming more components onto integrated circuits. J. Electron. 38(8), 183\u2013191 (1965)","journal-title":"J. Electron."},{"issue":"3","key":"8_CR15","doi-asserted-by":"publisher","first-page":"385","DOI":"10.2298\/FUEE1103385N","volume":"24","author":"N Nayeem","year":"2011","unstructured":"Nayeem, N., Rice, J.E.: A shared-cube approach to ESOP-based synthesis of reversible logic. Facta Universitatis of Ni\u00ca, Elec Energ. 24(3), 385\u2013402 (2011)","journal-title":"Facta Universitatis of Ni\u00ca, Elec Energ."},{"key":"8_CR16","unstructured":"Rice, J., Fazel, K., Thornton, M., Kent, K.: Toffoli gate cascade generation using ESOP minimization and QMDD-based swapping. In: Proceedings of 14th Reed-Muller Workshop, pp. 63\u201372 (2009)"},{"key":"8_CR17","doi-asserted-by":"crossref","unstructured":"Rice, J.E., Nayeem, N.: Ordering techniques for ESOP-based Toffoli cascade generation. In: Proceedings of IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), pp. 274\u2013279 (2011)","DOI":"10.1109\/PACRIM.2011.6032905"},{"key":"8_CR18","doi-asserted-by":"crossref","unstructured":"Rice, J.E., Suen, V.: Using autocorrelation coefficient-based cost functions in ESOP-based Toffoli gate cascade generation. In: Proceedings of 23rd Canadian Conference on Electrical and Computer Engineering (CCECE), pp. 1\u20136 (2010)","DOI":"10.1109\/CCECE.2010.5575167"},{"key":"8_CR19","doi-asserted-by":"crossref","unstructured":"Sanaee, Y., Dueck, GW.: Generating Toffoli networks from ESOP expressions. In: Proceedings of IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), pp. 715\u2013719 (2009)","DOI":"10.1109\/PACRIM.2009.5291282"},{"key":"8_CR20","doi-asserted-by":"crossref","unstructured":"Sanaee, Y., Dueck, G.W.: ESOP-based Toffoli network generation with transformations. In: Proceedings of 40th International Symposium on Multiple-Valued Logic, pp. 276\u2013281 (2010)","DOI":"10.1109\/ISMVL.2010.58"},{"key":"8_CR21","unstructured":"Soeken, M., Frehse, S., Wille, R., Drechsler, R.: Revkit: a toolkit for reversible circuit design. In: Proceedings of Workshop on Reversible Computation. Revkit is available at \n http:\/\/www.revkit.org\n \n (2010)"},{"key":"8_CR22","doi-asserted-by":"crossref","unstructured":"Wille,R., Drechsler, R.: BDD-based synthesis of reversible logic for large functions. In: Proceedings of Design Automation Conference, pp. 270\u2013275 (2009)","DOI":"10.1145\/1629911.1629984"},{"key":"8_CR23","doi-asserted-by":"crossref","unstructured":"Wille, R., Drechsler, R., Oswald, C., Garcia-Ortiz, A.: Automatic design of low-power encoders using reversible circuit synthesis. In: Proceedings of Design Automation Test in Europe (DATE), pp. 208\u2013212 (2012)","DOI":"10.1109\/DATE.2012.6176648"}],"container-title":["Advances in Intelligent Systems and Computing","Applied Computation and Security Systems"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-81-322-1988-0_8","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,27]],"date-time":"2019-05-27T13:36:46Z","timestamp":1558964206000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-81-322-1988-0_8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,8,27]]},"ISBN":["9788132219873","9788132219880"],"references-count":23,"URL":"http:\/\/dx.doi.org\/10.1007\/978-81-322-1988-0_8","relation":{},"ISSN":["2194-5357","2194-5365"],"issn-type":[{"type":"print","value":"2194-5357"},{"type":"electronic","value":"2194-5365"}],"subject":[],"published":{"date-parts":[[2014,8,27]]}}}